171 lines
7.3 KiB
C
171 lines
7.3 KiB
C
/****************************************************************************
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* arch/arm/include/armv7-m/irq_lazyfpu.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_ARMV7_M_IRQ_LAZYFPU_H
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#define __ARCH_ARM_INCLUDE_ARMV7_M_IRQ_LAZYFPU_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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/****************************************************************************
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* Pre-processor Prototypes
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****************************************************************************/
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/* IRQ Stack Frame Format: */
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/* The following additional registers are stored by the interrupt handling
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* logic.
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*/
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#define REG_R13 (0) /* R13 = SP at time of interrupt */
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#ifdef CONFIG_ARMV7M_USEBASEPRI
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# define REG_BASEPRI (1) /* BASEPRI */
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#else
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# define REG_PRIMASK (1) /* PRIMASK */
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#endif
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#define REG_R4 (2) /* R4 */
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#define REG_R5 (3) /* R5 */
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#define REG_R6 (4) /* R6 */
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#define REG_R7 (5) /* R7 */
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#define REG_R8 (6) /* R8 */
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#define REG_R9 (7) /* R9 */
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#define REG_R10 (8) /* R10 */
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#define REG_R11 (9) /* R11 */
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#ifdef CONFIG_BUILD_PROTECTED
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# define REG_EXC_RETURN (10) /* EXC_RETURN */
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# define SW_INT_REGS (11)
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#else
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# define SW_INT_REGS (10)
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#endif
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/* If the MCU supports a floating point unit, then it will be necessary
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* to save the state of the FPU status register and data registers on
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* each context switch. These registers are not saved during interrupt
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* level processing, however. So, as a consequence, floating point
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* operations may NOT be performed in interrupt handlers.
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*
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* The FPU provides an extension register file containing 32 single-
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* precision registers. These can be viewed as:
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*
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* - Sixteen 64-bit doubleword registers, D0-D15
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* - Thirty-two 32-bit single-word registers, S0-S31
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* S<2n> maps to the least significant half of D<n>
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* S<2n+1> maps to the most significant half of D<n>.
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*/
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#ifdef CONFIG_ARCH_FPU
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# define REG_D0 (SW_INT_REGS+0) /* D0 */
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# define REG_S0 (SW_INT_REGS+0) /* S0 */
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# define REG_S1 (SW_INT_REGS+1) /* S1 */
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# define REG_D1 (SW_INT_REGS+2) /* D1 */
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# define REG_S2 (SW_INT_REGS+2) /* S2 */
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# define REG_S3 (SW_INT_REGS+3) /* S3 */
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# define REG_D2 (SW_INT_REGS+4) /* D2 */
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# define REG_S4 (SW_INT_REGS+4) /* S4 */
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# define REG_S5 (SW_INT_REGS+5) /* S5 */
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# define REG_D3 (SW_INT_REGS+6) /* D3 */
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# define REG_S6 (SW_INT_REGS+6) /* S6 */
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# define REG_S7 (SW_INT_REGS+7) /* S7 */
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# define REG_D4 (SW_INT_REGS+8) /* D4 */
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# define REG_S8 (SW_INT_REGS+8) /* S8 */
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# define REG_S9 (SW_INT_REGS+9) /* S9 */
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# define REG_D5 (SW_INT_REGS+10) /* D5 */
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# define REG_S10 (SW_INT_REGS+10) /* S10 */
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# define REG_S11 (SW_INT_REGS+11) /* S11 */
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# define REG_D6 (SW_INT_REGS+12) /* D6 */
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# define REG_S12 (SW_INT_REGS+12) /* S12 */
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# define REG_S13 (SW_INT_REGS+13) /* S13 */
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# define REG_D7 (SW_INT_REGS+14) /* D7 */
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# define REG_S14 (SW_INT_REGS+14) /* S14 */
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# define REG_S15 (SW_INT_REGS+15) /* S15 */
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# define REG_D8 (SW_INT_REGS+16) /* D8 */
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# define REG_S16 (SW_INT_REGS+16) /* S16 */
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# define REG_S17 (SW_INT_REGS+17) /* S17 */
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# define REG_D9 (SW_INT_REGS+18) /* D9 */
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# define REG_S18 (SW_INT_REGS+18) /* S18 */
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# define REG_S19 (SW_INT_REGS+19) /* S19 */
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# define REG_D10 (SW_INT_REGS+20) /* D10 */
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# define REG_S20 (SW_INT_REGS+20) /* S20 */
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# define REG_S21 (SW_INT_REGS+21) /* S21 */
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# define REG_D11 (SW_INT_REGS+22) /* D11 */
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# define REG_S22 (SW_INT_REGS+22) /* S22 */
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# define REG_S23 (SW_INT_REGS+23) /* S23 */
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# define REG_D12 (SW_INT_REGS+24) /* D12 */
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# define REG_S24 (SW_INT_REGS+24) /* S24 */
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# define REG_S25 (SW_INT_REGS+25) /* S25 */
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# define REG_D13 (SW_INT_REGS+26) /* D13 */
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# define REG_S26 (SW_INT_REGS+26) /* S26 */
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# define REG_S27 (SW_INT_REGS+27) /* S27 */
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# define REG_D14 (SW_INT_REGS+28) /* D14 */
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# define REG_S28 (SW_INT_REGS+28) /* S28 */
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# define REG_S29 (SW_INT_REGS+29) /* S29 */
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# define REG_D15 (SW_INT_REGS+30) /* D15 */
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# define REG_S30 (SW_INT_REGS+30) /* S30 */
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# define REG_S31 (SW_INT_REGS+31) /* S31 */
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# define REG_FPSCR (SW_INT_REGS+32) /* Floating point status and control */
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# define SW_FPU_REGS (33)
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#else
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# define SW_FPU_REGS (0)
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#endif
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/* The total number of registers saved by software */
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#define SW_XCPT_REGS (SW_INT_REGS + SW_FPU_REGS)
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#define SW_XCPT_SIZE (4 * SW_XCPT_REGS)
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/* On entry into an IRQ, the hardware automatically saves the following
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* registers on the stack in this (address) order:
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*/
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#define REG_R0 (SW_XCPT_REGS+0) /* R0 */
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#define REG_R1 (SW_XCPT_REGS+1) /* R1 */
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#define REG_R2 (SW_XCPT_REGS+2) /* R2 */
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#define REG_R3 (SW_XCPT_REGS+3) /* R3 */
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#define REG_R12 (SW_XCPT_REGS+4) /* R12 */
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#define REG_R14 (SW_XCPT_REGS+5) /* R14 = LR */
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#define REG_R15 (SW_XCPT_REGS+6) /* R15 = PC */
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#define REG_XPSR (SW_XCPT_REGS+7) /* xPSR */
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#define HW_XCPT_REGS (8)
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#define HW_XCPT_SIZE (4 * HW_XCPT_REGS)
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#define XCPTCONTEXT_REGS (HW_XCPT_REGS + SW_XCPT_REGS)
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#define XCPTCONTEXT_SIZE (HW_XCPT_SIZE + SW_XCPT_SIZE)
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/****************************************************************************
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* Public Types
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****************************************************************************/
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/****************************************************************************
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* Inline functions
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****************************************************************************/
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#endif /* __ARCH_ARM_INCLUDE_ARMV7_M_IRQ_LAZYFPU_H */
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