400 lines
22 KiB
C
400 lines
22 KiB
C
/****************************************************************************
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* arch/arm/include/samv7/chip.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_SAMV7_CHIP_H
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#define __ARCH_ARM_INCLUDE_SAMV7_CHIP_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************
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* Pre-processor Prototypes
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****************************************************************************/
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/* Get customizations for each supported chip */
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/* SAME70Q19 - 512 Kbytes FLASH / 256 Kbytes SRAM
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* SAME70Q20 - 1024 Kbytes FLASH / 384 Kbytes SRAM
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* SAME70Q21 - 2048 Kbytes FLASH / 384 Kbytes SRAM
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*
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* LQFP144 and LFBGA144 packaging
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*/
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#if defined(CONFIG_ARCH_CHIP_SAME70Q19) || defined(CONFIG_ARCH_CHIP_SAME70Q20) || \
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defined(CONFIG_ARCH_CHIP_SAME70Q21)
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/* Internal memory */
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#if defined(CONFIG_ARCH_CHIP_SAME70Q19)
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# define SAMV7_FLASH_SIZE (512*1024) /* 512KB */
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# define SAMV7_SRAM_SIZE (256*1024) /* 256KB */
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#elif defined(CONFIG_ARCH_CHIP_SAME70Q20)
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# define SAMV7_FLASH_SIZE (1024*1024) /* 1024KB */
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# define SAMV7_SRAM_SIZE (384*1024) /* 384KB */
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#else /* if defined(CONFIG_ARCH_CHIP_SAME70Q21) */
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# define SAMV7_FLASH_SIZE (2048*1024) /* 2048KB */
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# define SAMV7_SRAM_SIZE (384*1024) /* 384KB */
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#endif
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# define SAMV7_BSRAM_SIZE (1*1024) /* 1KB Backup SRAM */
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/* Peripherals */
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# define SAMV7_NPIO 5 /* 5 PIO ports A-E */
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# define SAMV7_NEBI 1 /* Have External Bus Interface (EBI) */
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# define SAMV7_NSDRAMC 1 /* Have SDRAM controller (SDRAMC) */
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# define SAMV7_NMLB 0 /* No MediaLB interface (MLB) */
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# define SAMV7_NDMACHAN 24 /* 24 Central DMA Channels */
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# define SAMV7_NADC12 24 /* 24 12-bit ADC channels */
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# define SAMV7_NDAC12 2 /* 2 12-bit DAC channels */
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# define SAMV7_NTCCH 12 /* 12 Timer/counter channels */
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# define SAMV7_NTCCHIO 36 /* 36 Timer/counter channels I/O */
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# define SAMV7_NUSART 3 /* 3 USARTs */
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# define SAMV7_NUART 5 /* 5 UARTs */
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# define SAMV7_NQSPI 1 /* 1 Quad SPI */
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# define SAMV7_NSPI 2 /* 2 SPI, SPI0-1 */
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# define SAMV7_NTWIHS 3 /* 3 TWIHS */
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# define SAMV7_NHSMCI4 1 /* 1 4-bit HSMCI port */
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# define SAMV7_NCAN 2 /* 2 CAN ports */
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# define SAMV7_NEMAC 1 /* 1 Ethernet MAC (GMAC) */
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# define SAMV7_NEMACMII 1 /* 1 Ethernet MAC MII interface */
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# define SAMV7_NEMACRMII 1 /* 1 Ethernet MAC RMII interface */
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# define SAMV7_NISI12 1 /* 1 12-bit ISI interface */
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# define SAMV7_NISI8 0 /* No 8-bit ISI interface */
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# define SAMV7_NSSC 1 /* 1 SSC */
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# define SAMV7_NUDPHS 1 /* 1 USB high speed device */
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# define SAMV7_NUHPHS 1 /* 1 USB high speed embedded Mini-Host */
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# define SAMV7_NUDPFS 0 /* No USB full speed device */
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# define SAMV7_NUHPFS 0 /* No USB full speed embedded host */
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# define SAMV7_NACC 1 /* 1 Analog comparator */
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# define SAMV7_NETM 1 /* 1 Embedded Trace Macrocell (ETM) */
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/* SAME70N19 - 512 Kbytes FLASH / 256 Kbytes SRAM
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* SAME70N20 - 1024 Kbytes FLASH / 384 Kbytes SRAM
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* SAME70N21 - 2048 Kbytes FLASH / 384 Kbytes SRAM
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*
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* LQFP100 and TFBGA100 packaging
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*/
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#elif defined(CONFIG_ARCH_CHIP_SAME70N19) || defined(CONFIG_ARCH_CHIP_SAME70N20) || \
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defined(CONFIG_ARCH_CHIP_SAME70N21)
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/* Internal memory */
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#if defined(CONFIG_ARCH_CHIP_SAME70N19)
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# define SAMV7_FLASH_SIZE (512*1024) /* 512KB */
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# define SAMV7_SRAM_SIZE (256*1024) /* 256KB */
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#elif defined(CONFIG_ARCH_CHIP_SAME70N20)
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# define SAMV7_FLASH_SIZE (1024*1024) /* 1024KB */
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# define SAMV7_SRAM_SIZE (384*1024) /* 384KB */
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#else /* if defined(CONFIG_ARCH_CHIP_SAME70N21) */
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# define SAMV7_FLASH_SIZE (2048*1024) /* 2048KB */
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# define SAMV7_SRAM_SIZE (384*1024) /* 384KB */
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#endif
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# define SAMV7_BSRAM_SIZE (1*1024) /* 1KB Backup SRAM */
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/* Peripherals */
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# define SAMV7_NPIO 5 /* 5 PIO ports A-E */
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# define SAMV7_NEBI 0 /* No External Bus Interface (EBI) */
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# define SAMV7_NSDRAMC 0 /* No SDRAM controller (SDRAMC) */
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# define SAMV7_NMLB 0 /* No MediaLB interface (MLB) */
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# define SAMV7_NDMACHAN 24 /* 24 Central DMA Channels */
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# define SAMV7_NADC12 10 /* 10 12-bit ADC channels */
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# define SAMV7_NDAC12 2 /* 2 12-bit DAC channels */
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# define SAMV7_NTCCH 12 /* 12 Timer/counter channels */
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# define SAMV7_NTCCHIO 9 /* 9 Timer/counter channels I/O */
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# define SAMV7_NUSART 3 /* 3 USARTs */
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# define SAMV7_NUART 5 /* 5 UARTs */
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# define SAMV7_NQSPI 1 /* 1 Quad SPI */
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# define SAMV7_NSPI 1 /* 1 SPI, SPI0 only */
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# define SAMV7_NTWIHS 3 /* 3 TWIHS */
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# define SAMV7_NHSMCI4 1 /* 1 4-bit HSMCI port */
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# define SAMV7_NCAN 2 /* 2 CAN ports */
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# define SAMV7_NEMAC 1 /* 1 Ethernet MAC (GMAC) */
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# define SAMV7_NEMACMII 1 /* 1 Ethernet MAC MII interface */
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# define SAMV7_NEMACRMII 1 /* 1 Ethernet MAC RMII interface */
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# define SAMV7_NISI12 1 /* 1 12-bit ISI interface */
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# define SAMV7_NISI8 0 /* No 8-bit ISI interface */
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# define SAMV7_NSSC 1 /* 1 SSC */
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# define SAMV7_NUDPHS 1 /* 1 USB high speed device */
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# define SAMV7_NUHPHS 1 /* 1 USB high speed embedded Mini-Host */
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# define SAMV7_NUDPFS 0 /* No USB full speed device */
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# define SAMV7_NUHPFS 0 /* No USB full speed embedded host */
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# define SAMV7_NACC 1 /* 1 Analog comparator */
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# define SAMV7_NETM 1 /* 1 Embedded Trace Macrocell (ETM) */
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/* SAME70J19 - 512 Kbytes FLASH / 256 Kbytes SRAM
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* SAME70J20 - 1024 Kbytes FLASH / 384 Kbytes SRAM
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* SAME70J21 - 2048 Kbytes FLASH / 384 Kbytes SRAM
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*
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* LQFP64 and TFBGA64 packaging
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*/
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#elif defined(CONFIG_ARCH_CHIP_SAME70J19) || defined(CONFIG_ARCH_CHIP_SAME70J20) || \
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defined(CONFIG_ARCH_CHIP_SAME70J21)
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/* Internal memory */
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#if defined(CONFIG_ARCH_CHIP_SAME70J19)
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# define SAMV7_FLASH_SIZE (512*1024) /* 512KB */
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# define SAMV7_SRAM_SIZE (256*1024) /* 256KB */
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#elif defined(CONFIG_ARCH_CHIP_SAME70J20)
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# define SAMV7_FLASH_SIZE (1024*1024) /* 1024KB */
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# define SAMV7_SRAM_SIZE (384*1024) /* 384KB */
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#else /* if defined(CONFIG_ARCH_CHIP_SAME70J21) */
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# define SAMV7_FLASH_SIZE (2048*1024) /* 2048KB */
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# define SAMV7_SRAM_SIZE (384*1024) /* 384KB */
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#endif
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# define SAMV7_BSRAM_SIZE (1*1024) /* 1KB Backup SRAM */
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# define SAMV7_NPIO 5 /* 5 PIO ports A-E */
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# define SAMV7_NEBI 0 /* No External Bus Interface (EBI) */
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# define SAMV7_NSDRAMC 0 /* No SDRAM controller (SDRAMC) */
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# define SAMV7_NMLB 0 /* No MediaLB interface (MLB) */
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# define SAMV7_NDMACHAN 24 /* 24 Central DMA Channels */
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# define SAMV7_NADC12 5 /* 5 12-bit ADC channels */
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# define SAMV7_NDAC12 1 /* 1 12-bit DAC channel */
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# define SAMV7_NTCCH 12 /* 12 Timer/counter channels */
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# define SAMV7_NTCCHIO 3 /* 3 Timer/counter channels I/O */
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# define SAMV7_NUSART 0 /* No USARTs */
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# define SAMV7_NUART 5 /* 5 UARTs */
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# define SAMV7_NQSPI 0 /* No Quad SPI */
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# define SAMV7_NSPI 1 /* No SPI, QSPI functions in SPI mode only */
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# define SAMV7_NTWIHS 2 /* 2 TWIHS */
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# define SAMV7_NHSMCI4 0 /* No 4-bit HSMCI port */
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# define SAMV7_NCAN 1 /* 1 CAN port */
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# define SAMV7_NEMAC 1 /* 1 Ethernet MAC (GMAC) */
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# define SAMV7_NEMACMII 0 /* No Ethernet MAC MII interface */
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# define SAMV7_NEMACRMII 1 /* 1 Ethernet MAC RMII interface */
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# define SAMV7_NISI12 0 /* No 12-bit ISI interface */
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# define SAMV7_NISI8 1 /* 1 8-bit ISI interface */
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# define SAMV7_NSSC 1 /* 1 SSC */
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# define SAMV7_NUDPHS 0 /* No USB high speed device */
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# define SAMV7_NUHPHS 0 /* No USB high speed embedded Mini-Host */
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# define SAMV7_NUDPFS 1 /* 1 USB full speed device */
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# define SAMV7_NUHPFS 1 /* 1 USB full speed embedded host */
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# define SAMV7_NACC 1 /* 1 Analog comparator */
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# define SAMV7_NETM 1 /* 1 Embedded Trace Macrocell (ETM) */
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/* SAMV71Q19 - 512 Kbytes FLASH / 256 Kbytes SRAM
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* SAMV71Q20 - 1024 Kbytes FLASH / 384 Kbytes SRAM
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* SAMV71Q21 - 2048 Kbytes FLASH / 384 Kbytes SRAM
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*
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* LQFP144 and LFBGA144 packaging
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*/
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#elif defined(CONFIG_ARCH_CHIP_SAMV71Q19) || defined(CONFIG_ARCH_CHIP_SAMV71Q20) || \
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defined(CONFIG_ARCH_CHIP_SAMV71Q21)
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/* Internal memory */
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#if defined(CONFIG_ARCH_CHIP_SAMV71Q19)
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# define SAMV7_FLASH_SIZE (512*1024) /* 512KB */
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# define SAMV7_SRAM_SIZE (256*1024) /* 256KB */
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#elif defined(CONFIG_ARCH_CHIP_SAMV71Q20)
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# define SAMV7_FLASH_SIZE (1024*1024) /* 1024KB */
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# define SAMV7_SRAM_SIZE (384*1024) /* 384KB */
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#else /* if defined(CONFIG_ARCH_CHIP_SAMV71Q21) */
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# define SAMV7_FLASH_SIZE (2048*1024) /* 2048KB */
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# define SAMV7_SRAM_SIZE (384*1024) /* 384KB */
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#endif
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# define SAMV7_BSRAM_SIZE (1*1024) /* 1KB Backup SRAM */
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/* Peripherals */
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# define SAMV7_NPIO 5 /* 5 PIO ports A-E */
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# define SAMV7_NEBI 1 /* Have External Bus Interface (EBI) */
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# define SAMV7_NSDRAMC 1 /* Have SDRAM controller (SDRAMC) */
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# define SAMV7_NMLB 1 /* Have MediaLB interface (MLB) */
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# define SAMV7_NDMACHAN 24 /* 24 Central DMA Channels */
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# define SAMV7_NADC12 24 /* 24 12-bit ADC channels */
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# define SAMV7_NDAC12 2 /* 2 12-bit DAC channels */
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# define SAMV7_NTCCH 12 /* 12 Timer/counter channels */
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# define SAMV7_NTCCHIO 36 /* 36 Timer/counter channels I/O */
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# define SAMV7_NUSART 3 /* 3 USARTs */
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# define SAMV7_NUART 5 /* 5 UARTs */
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# define SAMV7_NQSPI 1 /* 1 Quad SPI */
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# define SAMV7_NSPI 2 /* 2 SPI, SPI0-1 */
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# define SAMV7_NTWIHS 3 /* 3 TWIHS */
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# define SAMV7_NHSMCI4 1 /* 1 4-bit HSMCI port */
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# define SAMV7_NCAN 2 /* 2 CAN ports */
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# define SAMV7_NEMAC 1 /* 1 Ethernet MAC (GMAC) */
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# define SAMV7_NEMACMII 1 /* 1 Ethernet MAC MII interface */
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# define SAMV7_NEMACRMII 1 /* 1 Ethernet MAC RMII interface */
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# define SAMV7_NISI12 1 /* 1 12-bit ISI interface */
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# define SAMV7_NISI8 0 /* No 8-bit ISI interface */
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# define SAMV7_NSSC 1 /* 1 SSC */
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# define SAMV7_NUDPHS 1 /* 1 USB high speed device */
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# define SAMV7_NUHPHS 1 /* 1 USB high speed embedded Mini-Host */
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# define SAMV7_NUDPFS 0 /* No USB full speed device */
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# define SAMV7_NUHPFS 0 /* No USB full speed embedded host */
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# define SAMV7_NACC 1 /* 1 Analog comparator */
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# define SAMV7_NETM 1 /* 1 Embedded Trace Macrocell (ETM) */
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/* SAMV71N19 - 512 Kbytes FLASH / 256 Kbytes SRAM
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* SAMV71N20 - 1024 Kbytes FLASH / 384 Kbytes SRAM
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* SAMV71N21 - 2048 Kbytes FLASH / 384 Kbytes SRAM
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*
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* LQFP100 and TFBGA100 packaging
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*/
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#elif defined(CONFIG_ARCH_CHIP_SAMV71N19) || defined(CONFIG_ARCH_CHIP_SAMV71N20) || \
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defined(CONFIG_ARCH_CHIP_SAMV71N21)
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/* Internal memory */
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#if defined(CONFIG_ARCH_CHIP_SAMV71N19)
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# define SAMV7_FLASH_SIZE (512*1024) /* 512KB */
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# define SAMV7_SRAM_SIZE (256*1024) /* 256KB */
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#elif defined(CONFIG_ARCH_CHIP_SAMV71N20)
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# define SAMV7_FLASH_SIZE (1024*1024) /* 1024KB */
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# define SAMV7_SRAM_SIZE (384*1024) /* 384KB */
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#else /* if defined(CONFIG_ARCH_CHIP_SAMV71N21) */
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# define SAMV7_FLASH_SIZE (2048*1024) /* 2048KB */
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# define SAMV7_SRAM_SIZE (384*1024) /* 384KB */
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#endif
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# define SAMV7_BSRAM_SIZE (1*1024) /* 1KB Backup SRAM */
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/* Peripherals */
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# define SAMV7_NPIO 5 /* 5 PIO ports A-E */
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# define SAMV7_NEBI 0 /* No External Bus Interface (EBI) */
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# define SAMV7_NSDRAMC 0 /* No SDRAM controller (SDRAMC) */
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# define SAMV7_NMLB 1 /* Have MediaLB interface (MLB) */
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# define SAMV7_NDMACHAN 24 /* 24 Central DMA Channels */
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# define SAMV7_NADC12 10 /* 10 12-bit ADC channels */
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# define SAMV7_NDAC12 2 /* 2 12-bit DAC channels */
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# define SAMV7_NTCCH 12 /* 12 Timer/counter channels */
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# define SAMV7_NTCCHIO 9 /* 9 Timer/counter channels I/O */
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# define SAMV7_NUSART 3 /* 3 USARTs */
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# define SAMV7_NUART 5 /* 5 UARTs */
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# define SAMV7_NQSPI 1 /* 1 Quad SPI */
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# define SAMV7_NSPI 1 /* 1 SPI, SPI0 */
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# define SAMV7_NTWIHS 3 /* 3 TWIHS */
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# define SAMV7_NHSMCI4 1 /* 1 4-bit HSMCI port */
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# define SAMV7_NCAN 2 /* 2 CAN ports */
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# define SAMV7_NEMAC 1 /* 1 Ethernet MAC (GMAC) */
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# define SAMV7_NEMACMII 1 /* 1 Ethernet MAC MII interface */
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# define SAMV7_NEMACRMII 1 /* 1 Ethernet MAC RMII interface */
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# define SAMV7_NISI12 1 /* 1 12-bit ISI interface */
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# define SAMV7_NISI8 0 /* No 8-bit ISI interface */
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# define SAMV7_NSSC 1 /* 1 SSC */
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# define SAMV7_NUDPHS 1 /* 1 USB high speed device */
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# define SAMV7_NUHPHS 1 /* 1 USB high speed embedded Mini-Host */
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# define SAMV7_NUDPFS 0 /* No USB full speed device */
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# define SAMV7_NUHPFS 0 /* No USB full speed embedded host */
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# define SAMV7_NACC 1 /* 1 Analog comparator */
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# define SAMV7_NETM 1 /* 1 Embedded Trace Macrocell (ETM) */
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/* SAMV71J19 - 512 Kbytes FLASH / 256 Kbytes SRAM
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* SAMV71J20 - 1024 Kbytes FLASH / 384 Kbytes SRAM
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* SAMV71J21 - 2048 Kbytes FLASH / 384 Kbytes SRAM
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*
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* LQFP64, TFBGA64, and QFN64 packaging
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*/
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#elif defined(CONFIG_ARCH_CHIP_SAMV71J19) || defined(CONFIG_ARCH_CHIP_SAMV71J20) || \
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defined(CONFIG_ARCH_CHIP_SAMV71J21)
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/* Internal memory */
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#if defined(CONFIG_ARCH_CHIP_SAMV71J19)
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# define SAMV7_FLASH_SIZE (512*1024) /* 512KB */
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# define SAMV7_SRAM_SIZE (256*1024) /* 256KB */
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#elif defined(CONFIG_ARCH_CHIP_SAMV71J20)
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# define SAMV7_FLASH_SIZE (1024*1024) /* 1024KB */
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# define SAMV7_SRAM_SIZE (384*1024) /* 384KB */
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#else /* if defined(CONFIG_ARCH_CHIP_SAMV71J21) */
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# define SAMV7_FLASH_SIZE (2048*1024) /* 2048KB */
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# define SAMV7_SRAM_SIZE (384*1024) /* 384KB */
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#endif
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#define SAMV7_BSRAM_SIZE (1*1024) /* 1KB Backup SRAM */
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/* Peripherals */
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# define SAMV7_NPIO 5 /* 5 PIO ports A-E */
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# define SAMV7_NEBI 0 /* No External Bus Interface (EBI) */
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# define SAMV7_NSDRAMC 0 /* No SDRAM controller (SDRAMC) */
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# define SAMV7_NMLB 1 /* Have MediaLB interface (MLB) */
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# define SAMV7_NDMACHAN 24 /* 24 Central DMA Channels */
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# define SAMV7_NADC12 5 /* 5 12-bit ADC channels */
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# define SAMV7_NDAC12 1 /* 1 12-bit DAC channels */
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# define SAMV7_NTCCH 12 /* 12 Timer/counter channels */
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# define SAMV7_NTCCHIO 3 /* 3 Timer/counter channels I/O */
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# define SAMV7_NUSART 0 /* No USARTs */
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# define SAMV7_NUART 5 /* 5 UARTs */
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# define SAMV7_NQSPI 0 /* No Quad SPI */
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# define SAMV7_NSPI 1 /* 1 SPI, QSPI functions in SPI mode only */
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# define SAMV7_NTWIHS 2 /* 2 TWIHS */
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# define SAMV7_NHSMCI4 0 /* No 4-bit HSMCI port */
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# define SAMV7_NCAN 1 /* 1 CAN port */
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# define SAMV7_NEMAC 1 /* 1 Ethernet MAC (GMAC) */
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# define SAMV7_NEMACMII 0 /* No Ethernet MAC MII interface */
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# define SAMV7_NEMACRMII 1 /* 1 Ethernet MAC RMII interface */
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# define SAMV7_NISI12 0 /* No 12-bit ISI interface */
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# define SAMV7_NISI8 1 /* 1 8-bit ISI interface */
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# define SAMV7_NSSC 1 /* 1 SSC */
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# define SAMV7_NUDPHS 0 /* No USB high speed device */
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# define SAMV7_NUHPHS 0 /* No USB high speed embedded Mini-Host */
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# define SAMV7_NUDPFS 1 /* 1 USB full speed device */
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# define SAMV7_NUHPFS 1 /* 1 USB full speed embedded host */
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# define SAMV7_NACC 1 /* 1 Analog comparator */
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# define SAMV7_NETM 1 /* 1 Embedded Trace Macrocell (ETM) */
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#else
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# error "Unknown SAMV7 chip type"
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#endif
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/* NVIC priority levels *****************************************************/
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/* Each priority field holds a priority value, 0-15. The lower the value, the
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* greater the priority of the corresponding interrupt. The processor
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* implements only bits[7:6] of each field, bits[5:0] read as zero and ignore
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* writes.
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*/
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#define NVIC_SYSH_PRIORITY_MIN 0xc0 /* All bits[7:6] set is minimum priority */
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#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
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#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
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#define NVIC_SYSH_PRIORITY_STEP 0x40 /* Two bits of interrupt priority used */
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/****************************************************************************
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* Public Types
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****************************************************************************/
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Public Functions Prototypes
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****************************************************************************/
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#endif /* __ARCH_ARM_INCLUDE_SAMV7_CHIP_H */
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