350 lines
15 KiB
C
350 lines
15 KiB
C
/****************************************************************************
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* arch/arm/src/samd2l2/sam_dmac.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAMD2L2_SAM_DMAC_H
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#define __ARCH_ARM_SRC_SAMD2L2_SAM_DMAC_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include "chip.h"
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#include "hardware/sam_dmac.h"
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#ifdef CONFIG_SAMD2L2_DMAC
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#if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
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# include "hardware/samd_dmac.h"
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#elif defined(CONFIG_ARCH_FAMILY_SAML21)
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# include "hardware/saml_dmac.h"
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#else
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# error Unrecognized SAMD/L architecture
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* DMA **********************************************************************/
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/* Flags used to characterize the desired DMA channel. The naming convention
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* is that one side is the peripheral and the other is memory (however, the
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* interface could still be used if, for example, both sides were memory
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* although the naming would be awkward)
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*/
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/* Common characteristics
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*
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* BEATSIZE - The size of one bus transfer or "beat". 8-, 16-,
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* or 32-bits
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* STEPSIZE - When the address is incremented, it is increments
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* by how many "beats"?
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* STEPSEL - The STEPSIZE may be applied only to the memory to
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* the peripheral.
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*/
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#define DMACH_FLAG_BEATSIZE_SHIFT (0) /* Bits 0-1: Beat size */
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#define DMACH_FLAG_BEATSIZE_MASK (3 << DMACH_FLAG_BEATSIZE_SHIFT)
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# define DMACH_FLAG_BEATSIZE_BYTE (0 << DMACH_FLAG_BEATSIZE_SHIFT) /* 8-bit bus transfer */
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# define DMACH_FLAG_BEATSIZE_HWORD (1 << DMACH_FLAG_BEATSIZE_SHIFT) /* 16-bit bus transfer */
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# define DMACH_FLAG_BEATSIZE_WORD (2 << DMACH_FLAG_BEATSIZE_SHIFT) /* 32-bit bus transfer */
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#define DMACH_FLAG_STEPSEL (1 << 2) /* Bit 2: Step selection */
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# define DMACH_FLAG_STEPSEL_MEM (0) /* 0=Step size applies to memory */
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# define DMACH_FLAG_STEPSEL_PERIPH (1 << 2) /* 1=Step size applies to peripheral */
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#define DMACH_FLAG_STEPSIZE_SHIFT (3) /* Bits 3-5: Address increment step */
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#define DMACH_FLAG_STEPSIZE_MASK (7 << DMACH_FLAG_STEPSIZE_SHIFT)
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# define DMACH_FLAG_STEPSIZE_X1 (0 << DMACH_FLAG_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 1 */
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# define DMACH_FLAG_STEPSIZE_X2 (1 << DMACH_FLAG_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 2 */
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# define DMACH_FLAG_STEPSIZE_X4 (2 << DMACH_FLAG_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 4 */
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# define DMACH_FLAG_STEPSIZE_X8 (3 << DMACH_FLAG_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 8 */
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# define DMACH_FLAG_STEPSIZE_X16 (4 << DMACH_FLAG_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 16 */
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# define DMACH_FLAG_STEPSIZE_X32 (5 << DMACH_FLAG_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 32 */
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# define DMACH_FLAG_STEPSIZE_X64 (6 << DMACH_FLAG_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 64 */
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# define DMACH_FLAG_STEPSIZE_X128 (7 << DMACH_FLAG_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 128 */
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#define DMACH_FLAG_PRIORITY_SHIFT (6) /* Bit 6-7: Arbitration priority */
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#define DMACH_FLAG_PRIORITY_MASK (3 << DMACH_FLAG_PRIORITY_SHIFT)
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# define DMACH_FLAG_PRIORITY(n) ((uint32_t)(n) << DMACH_FLAG_PRIORITY_SHIFT)
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#define DMACH_FLAG_RUNINSTDBY (1 << 8) /* Bit 8: Run in standby */
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/* Peripheral endpoint characteristics.
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*
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* PERIPH_TXTRIG - The TX ID of the peripheral that provides the DMA
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* trigger.
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* This is one of the DMA_TRIGSRC_*[_TX] definitions.
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* This trigger source is selected when sam_dmatxsetup()
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* is called.
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* PERIPH_RXTRIG - The RX ID of the peripheral that provides the DMA
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* trigger.
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* This is one of the DMA_TRIGSRC_*[_RX] definitions.
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* This trigger source is selected when sam_dmarxsetup()
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* is called.
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* PERIPH_INCREMENT - Indicates that the peripheral address should be
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* incremented on each "beat"
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* PERIPH_QOS - Quality of service for peripheral accesses
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*/
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#define DMACH_FLAG_PERIPH_TXTRIG_SHIFT (9) /* Bits 9-14: See DMAC_TRIGSRC_*[_TX] */
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#define DMACH_FLAG_PERIPH_TXTRIG_MASK (0x3f << DMACH_FLAG_PERIPH_TXTRIG_SHIFT)
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# define DMACH_FLAG_PERIPH_TXTRIG(n) ((uint32_t)(n) << DMACH_FLAG_PERIPH_TXTRIG_SHIFT)
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#define DMACH_FLAG_PERIPH_RXTRIG_SHIFT (15) /* Bits 15-20: See DMAC_TRIGSRC_*[_RX] */
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#define DMACH_FLAG_PERIPH_RXTRIG_MASK (0x3f << DMACH_FLAG_PERIPH_RXTRIG_SHIFT)
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# define DMACH_FLAG_PERIPH_RXTRIG(n) ((uint32_t)(n) << DMACH_FLAG_PERIPH_RXTRIG_SHIFT)
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#define DMACH_FLAG_PERIPH_INCREMENT (1 << 21) /* Bit 21: Autoincrement peripheral address */
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#define DMACH_FLAG_PERIPH_QOS_SHIFT (22) /* Bits 22-23: Peripheral quality of service */
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#define DMACH_FLAG_PERIPH_QOS_MASK (3 << DMACH_FLAG_PERIPH_QOS_SHIFT)
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# define DMACH_FLAG_PERIPH_QOS_DISABLE (0 << DMACH_FLAG_PERIPH_QOS_SHIFT) /* Background */
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# define DMACH_FLAG_PERIPH_QOS_LOW (1 << DMACH_FLAG_PERIPH_QOS_SHIFT) /* Sensitive bandwidth */
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# define DMACH_FLAG_PERIPH_QOS_MEDIUM (2 << DMACH_FLAG_PERIPH_QOS_SHIFT) /* Sensitive latency */
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# define DMACH_FLAG_PERIPH_QOS_HIGH (3 << DMACH_FLAG_PERIPH_QOS_SHIFT) /* Critical latency */
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/* Memory endpoint characteristics
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*
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* MEM_INCREMENT - Indicates that the memory address should be incremented on
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* each "beat"
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* MEM_QOS - Quality of service for memory accesses
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*/
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#define DMACH_FLAG_MEM_INCREMENT (1 << 24) /* Bit 24: Autoincrement memory address */
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#define DMACH_FLAG_MEM_QOS_SHIFT (25) /* Bits 25-26: Memory quality of service */
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#define DMACH_FLAG_MEM_QOS_MASK (3 << DMACH_FLAG_MEM_QOS_SHIFT)
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# define DMACH_FLAG_MEM_QOS_DISABLE (0 << DMACH_FLAG_MEM_QOS_SHIFT) /* Background */
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# define DMACH_FLAG_MEM_QOS_LOW (1 << DMACH_FLAG_MEM_QOS_SHIFT) /* Sensitive bandwidth */
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# define DMACH_FLAG_MEM_QOS_MEDIUM (2 << DMACH_FLAG_MEM_QOS_SHIFT) /* Sensitive latency */
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# define DMACH_FLAG_MEM_QOS_HIGH (3 << DMACH_FLAG_MEM_QOS_SHIFT) /* Critical latency */
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/* Bits 27-31: Not used */
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/****************************************************************************
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* Public Types
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****************************************************************************/
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typedef void *DMA_HANDLE;
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typedef void (*dma_callback_t)(DMA_HANDLE handle, void *arg, int result);
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/* The following is used for sampling DMA registers when CONFIG DEBUG_DMA
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* is selected
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*/
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#ifdef CONFIG_DEBUG_DMA_INFO
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struct sam_dmaregs_s
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{
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/* DMAC Registers */
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uint8_t crcstatus; /* CRC Status Register */
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uint8_t dbgctrl; /* Debug Control Register */
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uint8_t qosctrl; /* Quality of Service Control Register */
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uint8_t chid; /* Channel ID Register */
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uint8_t chctrla; /* Channel Control A Register */
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uint8_t chintflag; /* Channel Interrupt Flag Status and Clear Register */
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uint8_t chstatus; /* Channel Status Register */
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uint16_t ctrl; /* Control Register */
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uint16_t crcctrl; /* CRC Control Register */
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uint16_t intpend; /* Interrupt Pending Register */
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uint32_t crcdatain; /* CRC Data Input Register */
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uint32_t crcchksum; /* CRC Checksum Register */
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uint32_t swtrigctrl; /* Software Trigger Control Register */
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uint32_t prictrl0; /* Priority Control 0 Register */
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uint32_t intstatus; /* Interrupt Status Register */
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uint32_t busych; /* Busy Channels Register */
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uint32_t pendch; /* Pending Channels Register */
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uint32_t active; /* Active Channels and Levels Register */
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uint32_t baseaddr; /* Descriptor Memory Section Base Address Register */
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uint32_t wrbaddr; /* Write-Back Memory Section Base Address Register */
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uint32_t chctrlb; /* Channel Control B Register */
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};
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#endif
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/****************************************************************************
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* Inline Functions
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****************************************************************************/
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#ifndef __ASSEMBLY__
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/****************************************************************************
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* Public Data
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****************************************************************************/
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#undef EXTERN
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#if defined(__cplusplus)
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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/****************************************************************************
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* Name: sam_dmachannel
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*
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* Description:
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* Allocate a DMA channel.
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* This function sets aside a DMA channel and gives the caller exclusive
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* access to the DMA channel.
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*
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* The naming convention in all of the DMA interfaces is that one side is
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* the 'peripheral' and the other is 'memory'. However, the interface
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* could still be used if, for example, both sides were memory although
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* the naming would be awkward.
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*
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* Returned Value:
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* If a DMA channel if the required FIFO size is available, this function
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* returns a non-NULL, void* DMA channel handle.
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* NULL is returned on any failure.
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*
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****************************************************************************/
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DMA_HANDLE sam_dmachannel(uint32_t chflags);
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/****************************************************************************
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* Name: sam_dmaconfig
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*
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* Description:
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* There are two channel usage models: (1) The channel is allocated and
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* configured in one step. This is the typical case where a DMA channel
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* performs a constant role. The alternative is (2) where the DMA channel
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* is reconfigured on the fly. In this case, the chflags provided to
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* sam_dmachannel are not used and sam_dmaconfig() is called before each
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* DMA to configure the DMA channel appropriately.
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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void sam_dmaconfig(DMA_HANDLE handle, uint32_t chflags);
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/****************************************************************************
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* Name: sam_dmafree
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*
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* Description:
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* Release a DMA channel.
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* NOTE: The 'handle' used in this argument must NEVER be used again until
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* sam_dmachannel() is called again to re-gain a valid handle.
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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void sam_dmafree(DMA_HANDLE handle);
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/****************************************************************************
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* Name: sam_dmatxsetup
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*
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* Description:
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* Configure DMA for transmit of one buffer (memory to peripheral).
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* This function may be called multiple times to handle large and/or
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* non-contiguous transfers.
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* Calls to sam_dmatxsetup() and sam_dmarxsetup() must not be intermixed
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* on the same transfer, however.
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*
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****************************************************************************/
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int sam_dmatxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
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size_t nbytes);
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/****************************************************************************
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* Name: sam_dmarxsetup
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*
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* Description:
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* Configure DMA for receipt of one buffer (peripheral to memory).
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* This function may be called multiple times to handle large and/or
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* non-contiguous transfers.
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* Calls to sam_dmatxsetup() and sam_dmarxsetup() must not be intermixed
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* on the same transfer, however.
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*
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****************************************************************************/
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int sam_dmarxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
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size_t nbytes);
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/****************************************************************************
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* Name: sam_dmastart
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*
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* Description:
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* Start the DMA transfer
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*
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****************************************************************************/
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int sam_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg);
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/****************************************************************************
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* Name: sam_dmastop
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*
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* Description:
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* Cancel the DMA. After sam_dmastop() is called, the DMA channel is
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* reset and sam_dmarx/txsetup() must be called before sam_dmastart()
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* can be called again
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*
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****************************************************************************/
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void sam_dmastop(DMA_HANDLE handle);
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/****************************************************************************
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* Name: sam_dmasample
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*
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* Description:
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* Sample DMA register contents
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*
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****************************************************************************/
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#ifdef CONFIG_DEBUG_DMA_INFO
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void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs);
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#else
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# define sam_dmasample(handle,regs)
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#endif
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/****************************************************************************
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* Name: sam_dmadump
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*
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* Description:
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* Dump previously sampled DMA register contents
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*
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****************************************************************************/
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#ifdef CONFIG_DEBUG_DMA_INFO
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void sam_dmadump(DMA_HANDLE handle, const struct sam_dmaregs_s *regs,
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const char *msg);
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#else
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# define sam_dmadump(handle,regs,msg)
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#endif
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#undef EXTERN
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#if defined(__cplusplus)
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* CONFIG_SAMD2L2_DMAC */
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#endif /* __ARCH_ARM_SRC_SAMD2L2_SAM_DMAC_H */
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