165 lines
4.4 KiB
Plaintext
165 lines
4.4 KiB
Plaintext
/****************************************************************************
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* boards/arm64/zynq-mpsoc/zcu111/scripts/dramboot.ld
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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OUTPUT_ARCH(aarch64)
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ENTRY(__start)
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/* We don't use Uboot on Zynq UltraScale+ MPSoC besause XilinX SDK provided
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* FSBL(First Stage Boot Loader) which will boot ATF(Trusted Firmware-A)
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* and ATF will boot NuttX on BL31 stage. Memory is organized as follows:
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* - ATF debug reserved area is 0x00000000 - 0x00100000
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* - NuttX is loaded to 0x00100000 by ATF, ATF expects us here
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* - NuttX ROM and RAM are one continuous region, starting from 0x00100000
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with a size of 2046MB
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* - Heap memory is allocated from dram end to idlestack top
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*/
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MEMORY
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{
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axi_bram_ctrl_0_Mem0 : ORIGIN = 0xB0000000, LENGTH = 0x1000
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psu_ddr_0_MEM_0 : ORIGIN = 0x0, LENGTH = 0x100000
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dram (rwx) : ORIGIN = 0x00100000, LENGTH = 0x7FE00000
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psu_ddr_1_MEM_0 : ORIGIN = 0x800000000, LENGTH = 0x80000000
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psu_ocm_ram_0_MEM_0 : ORIGIN = 0xFFFC0000, LENGTH = 0x40000
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psu_qspi_linear_0_MEM_0 : ORIGIN = 0xC0000000, LENGTH = 0x20000000
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}
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PHDRS
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{
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/* R = 100, W = 010, X = 001 */
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text PT_LOAD FLAGS(5); /* RX */
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rodata PT_LOAD FLAGS(4); /* R */
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data PT_LOAD FLAGS(6); /* RW */
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}
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SECTIONS
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{
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.text :
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{
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_stext = ABSOLUTE(.); /* Text section */
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*(.start .start.*) /* Place __start here */
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*(.text .text.*)
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*(.text.cold)
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*(.text.unlikely)
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*(.fixup)
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*(.gnu.warning)
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} > dram :text
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.init_section :
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{
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_sinit = ABSOLUTE(.);
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KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
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KEEP(*(.init_array .ctors))
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_einit = ABSOLUTE(.);
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} > dram :text
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/* Vector table must be page aligned */
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.vector : ALIGN(4096)
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{
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_vector_start = ABSOLUTE(.);
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KEEP(*(.exc_vector_table))
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KEEP(*(".exc_vector_table.*"))
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KEEP(*(.vectors))
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_vector_end = ABSOLUTE(.);
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} > dram :text
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/* End of text data must be aligned to page boundary */
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. = ALIGN(4096);
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_etext = .;
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_sztext = _etext - _stext;
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/* Start of RO data must be page aligned (mapped as read only) */
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.rodata : ALIGN(4096)
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{
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_srodata = ABSOLUTE(.); /* Read-only data */
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*(.rodata .rodata.*)
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*(.data.rel.ro)
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*(.data.rel.ro.*)
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} > dram :rodata
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/* End of RO data must be page aligned */
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. = ALIGN(4096);
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_erodata = .; /* End of read-only data */
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_szrodata = _erodata - _srodata;
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_eronly = .; /* End of read-only data */
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.data : ALIGN(4096)
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{
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_sdata = ABSOLUTE(.);
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*(.data.page_aligned)
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*(.data .data.*)
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. = ALIGN(8);
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*(.data.rel)
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*(.data.rel.*)
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CONSTRUCTORS
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. = ALIGN(8);
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_edata = ABSOLUTE(.);
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} > dram :data
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.bss :
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{
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. = ALIGN(8);
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_sbss = ABSOLUTE(.);
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*(.bss .bss.*)
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. = ALIGN(8);
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_ebss = ABSOLUTE(.);
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} > dram :data
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_szbss = _ebss - _sbss;
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.initstack :
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{
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_s_initstack = ABSOLUTE(.);
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*(.initstack)
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} > dram :data
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/* End of data must be page aligned */
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. = ALIGN(4096);
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g_idle_topstack = .;
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_e_initstack = .;
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_szdata = _e_initstack - _sdata;
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/* Sections to be discarded */
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/DISCARD/ : {
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*(.exit.text)
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*(.exit.data)
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*(.exitcall.exit)
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*(.eh_frame)
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}
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/* Stabs debugging sections. */
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.stab 0 : { *(.stab) }
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.stabstr 0 : { *(.stabstr) }
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.stab.excl 0 : { *(.stab.excl) }
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.stab.exclstr 0 : { *(.stab.exclstr) }
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.stab.index 0 : { *(.stab.index) }
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.stab.indexstr 0 : { *(.stab.indexstr) }
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.comment 0 : { *(.comment) }
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}
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