Huang Qi 6ea3bc1217 riscv/debug: Add support for steppoint
Steppoint can be implemented by icount(instruction count)
from RISC-V debug extension, but it may not implemented in all RISC-V cores.

Unfortunately, the currently supported RISC-V cores do not implement it.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2024-08-01 13:57:51 +08:00
..
2024-07-30 18:23:19 +08:00
2024-07-15 02:29:30 +08:00
2024-07-15 02:29:30 +08:00