347 lines
13 KiB
C
347 lines
13 KiB
C
/****************************************************************************
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* boards/arm/sama5/sama5d3x-ek/include/board.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __BOARDS_ARM_SAMA5_SAMA5D3X_EK_INCLUDE_BOARD_H
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#define __BOARDS_ARM_SAMA5_SAMA5D3X_EK_INCLUDE_BOARD_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/irq.h>
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/* Clocking *****************************************************************/
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/* After power-on reset, the SAMA5 device is running on a 12MHz internal RC.
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* These definitions will configure operational clocking.
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*/
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/* On-board crystal frequencies */
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#define BOARD_MAINOSC_FREQUENCY (12000000) /* MAINOSC: 12MHz crystal on-board */
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#define BOARD_SLOWCLK_FREQUENCY (32768) /* Slow Clock: 32.768KHz */
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#if defined(CONFIG_SAMA5_BOOT_SDRAM)
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/* When booting from SDRAM, NuttX is loaded in SDRAM by an intermediate
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* bootloader.
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* That bootloader had to have already configured the PLL and SDRAM for
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* proper operation.
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*
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* In this case, we don not reconfigure the clocking.
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* Rather, we need to query the register settings to determine the clock
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* frequencies. We can only assume that the Main clock source is the
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* on-board 12MHz crystal.
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*/
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# include <arch/board/board_sdram.h>
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#elif defined(CONFIG_SAMA5D3xEK_384MHZ)
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/* OHCI Only.
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* This is an alternative slower configuration that will produce a 48MHz
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* USB clock with the required accuracy using only PLLA.
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* When PPLA is used to clock OHCI, an additional requirement is the PLLACK
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* be a multiple of 48MHz.
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* This setup results in a CPU clock of 384MHz.
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*
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* This case is only interesting for experimentation.
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*/
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# include <arch/board/board_384mhz.h>
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#elif defined(CONFIG_SAMA5D3xEK_528MHZ)
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/* This is the configuration results in a CPU clock of 528MHz.
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*
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* In this configuration, UPLL is the source of the UHPHS clock (if enabled).
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*/
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# include <arch/board/board_528mhz.h>
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#else /* #elif defined(CONFIG_SAMA5D3xEK_396MHZ) */
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/* This is the configuration provided in the Atmel example code.
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* This setup results in a CPU clock of 396MHz.
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*
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* In this configuration, UPLL is the source of the UHPHS clock (if enabled).
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*/
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# include <arch/board/board_396mhz.h>
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* LCD Interface, Geometry and Timing */
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#define BOARD_LCDC_OUTPUT_BPP 24 /* Output format to H/W is 24BPP RGB */
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#define BOARD_LCDC_WIDTH 800 /* Display width (pixels) */
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#define BOARD_LCDC_HEIGHT 480 /* Display height (rows) */
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#undef BOARD_LCDC_MCK_MUL2 /* Source clock is Mck (vs 2*Mck) */
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#define BOARD_LCDC_PIXCLK_INV 1 /* Invert pixel clock, use falling edge */
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#define BOARD_LCDC_PIXELCLOCK 33260000 /* Pixel clock frequency */
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#define BOARD_LCDC_GUARDTIME 9 /* Guard time (frames) */
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#define BOARD_LCDC_VSPW 2 /* Vertical pulse width (lines) */
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#define BOARD_LCDC_HSPW 128 /* Horizontal pulse width (LCDDOTCLK) */
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#define BOARD_LCDC_VFPW 37 /* Vertical front porch (lines) */
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#define BOARD_LCDC_VBPW 8 /* Vertical back porch (lines) */
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#define BOARD_LCDC_HFPW 168 /* Horizontal front porch (LCDDOTCLK) */
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#define BOARD_LCDC_HBPW 88 /* Horizontal back porch (LCDDOTCLK) */
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/* Backlight prescaler value and PWM output polarity */
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#define BOARD_LCDC_PWMPS LCDC_LCDCFG6_PWMPS_DIV1
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#define BOARD_LCDC_PWMPOL LCDC_LCDCFG6_PWMPOL
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/* LED definitions **********************************************************/
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/* There are two LEDs on the SAMA5D3 series-CM board that can be controlled
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* by software. A blue LED is controlled via PIO pins. A red LED normally
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* provides an indication that power is supplied to the board but can also
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* be controlled via software.
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*
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* PE25. This blue LED is pulled high and is illuminated by pulling PE25
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* low.
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*
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* PE24. The red LED is also pulled high but is driven by a transistor so
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* that it is illuminated when power is applied even if PE24 is not
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* configured as an output. If PE24 is configured as an output, then the
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* LCD is illuminated by a high output.
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*/
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/* LED index values for use with board_userled() */
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#define BOARD_BLUE 0
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#ifdef CONFIG_SAMA5D3xEK_NOREDLED
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# define BOARD_NLEDS 1
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#else
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# define BOARD_RED 1
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# define BOARD_NLEDS 2
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#endif
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/* LED bits for use with board_userled_all() */
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#define BOARD_BLUE_BIT (1 << BOARD_BLUE)
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#ifndef CONFIG_SAMA5D3xEK_NOREDLED
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# define BOARD_RED_BIT (1 << BOARD_RED)
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#endif
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/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is
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* defined. In that case, the usage by the board port is defined in
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* include/board.h and src/sam_leds.c. The LEDs are used to encode OS-related
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* events as follows when the red LED (PE24) is available:
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*
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* SYMBOL Val Meaning LED state
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* Blue Red
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* ----------------- --- ----------------------- -------- --------
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*/
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#define LED_STARTED 0 /* NuttX has been started OFF OFF */
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#define LED_HEAPALLOCATE 0 /* Heap has been allocated OFF OFF */
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#define LED_IRQSENABLED 0 /* Interrupts enabled OFF OFF */
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#define LED_STACKCREATED 1 /* Idle stack created ON OFF */
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#define LED_INIRQ 2 /* In an interrupt No change */
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#define LED_SIGNAL 2 /* In a signal handler No change */
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#define LED_ASSERTION 2 /* An assertion failed No change */
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#define LED_PANIC 3 /* The system has crashed OFF Blinking */
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#undef LED_IDLE /* MCU is is sleep mode Not used */
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/* If CONFIG_SAMA5D3xEK_NOREDLED=y, then the red LED is not used by the
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* system. The only difference from the above is that it is the blue, not
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* the red LED that blinks in the event of an PANIC.
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*
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* Thus if the blue LED is statically on, NuttX has successfully booted and
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* is, apparently, running normally. If the red (or blue) LED is flashing
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* at approximately 2Hz, then a fatal error has been detected and the system
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* has halted.
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*/
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/* Button definitions *******************************************************/
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/* There are five push button switches on the SAMA5D3X-EK base board:
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*
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* 1. One Reset, board reset (BP1)
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* 2. One Wake up, push button to bring the processor out of low power mode
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* (BP2)
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* 3. One User momentary Push Button
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* 4. One Disable CS Push Button
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*
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* Only the momentary push button is controllable by software (labelled
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* "PB_USER1" on the board):
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*
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* - PE27. Pressing the switch connect PE27 to grounded. Therefore, PE27
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* must be pulled high internally. When the button is pressed the SAMA5
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* will sense "0" is on PE27.
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*/
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#define BUTTON_USER1 0
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#define NUM_BUTTONS 1
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#define BUTTON_USER1_BIT (1 << BUTTON_USER1)
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/* NAND *********************************************************************/
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/* Address for transferring command bytes to the nandflash, CLE A22 */
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#define BOARD_EBICS3_NAND_CMDADDR 0x60400000
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/* Address for transferring address bytes to the nandflash, ALE A21 */
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#define BOARD_EBICS3_NAND_ADDRADDR 0x60200000
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/* Address for transferring data bytes to the nandflash. */
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#define BOARD_EBICS3_NAND_DATAADDR 0x60000000
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/* PIO configuration ********************************************************/
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/* LCDC */
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#define PIO_LCD_DAT16 PIO_LCD_DAT16_2
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#define PIO_LCD_DAT17 PIO_LCD_DAT17_2
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#define PIO_LCD_DAT18 PIO_LCD_DAT18_2
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#define PIO_LCD_DAT19 PIO_LCD_DAT19_2
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#define PIO_LCD_DAT20 PIO_LCD_DAT20_2
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#define PIO_LCD_DAT21 PIO_LCD_DAT21_2
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#define PIO_LCD_DAT22 PIO_LCD_DAT22_1
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#define PIO_LCD_DAT23 PIO_LCD_DAT23_1
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/* PWM.
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* There are no dedicated PWM output pins available to the user for PWM
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* testing.
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* Care must be taken because all PWM output pins conflict with some other
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* usage of the pin by other devices. Furthermore, many of these pins have
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* not been brought out to an external connector:
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*
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* -----+---+---+----+------+----------------
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* PWM PIN PER PIO I/O CONFLICTS
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* -----+---+---+----+------+----------------
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* PWM0 FI B PC28 J2.30 SPI1, ISI
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* H B PB0 --- GMAC
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* B PA20 J1.14 LCDC, ISI
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* L B PB1 --- GMAC
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* B PA21 J1.16 LCDC, ISI
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* -----+---+---+----+------+----------------
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* PWM1 FI B PC31 J2.36 HDMI
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* H B PB4 --- GMAC
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* B PA22 J1.18 LCDC, ISI
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* L B PB5 --- GMAC
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* B PE31 J3.20 ISI, HDMI
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* B PA23 J1.20 LCDC, ISI
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* -----+---+---+----+------+----------------
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* PWM2 FI B PC29 J2.29 UART0, ISI, HDMI
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* H C PD5 --- HSMCI0
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* B PB8 --- GMAC
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* L C PD6 --- HSMCI0
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* B PB9 --- GMAC
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* -----+---+---+----+------+----------------
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* PWM3 FI C PD16 --- SPI0, Audio
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* H C PD7 --- HSMCI0
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* B PB12 J3.7 GMAC
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* L C PD8 --- HSMCI0
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* B PB13 --- GMAC
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* -----+---+---+----+------+----------------
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*/
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/* PWM channel 0:
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*
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* PA20 and PA21 can be used if the LCDC or ISI are not selected.
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* These outputs are available on J1, pins 14 and 16, respectively.
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*
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* If the GMAC is not selected, then PB0 and PB1 could also be used.
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* However, these pins are not available at the I/O expansion connectors.
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*/
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#if !defined(CONFIG_SAMA5_LCDC) && !defined(CONFIG_SAMA5_ISI)
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# define PIO_PWM0_H PIO_PWM0_H_2
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# define PIO_PWM0_L PIO_PWM0_L_2
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#elif !defined(CONFIG_SAMA5_GMAC)
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# define PIO_PWM0_H PIO_PWM0_H_1
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# define PIO_PWM0_L PIO_PWM0_L_1
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#endif
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/* PWM channel 1:
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*
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* PA22 and PA23 can be used if the LCDC or ISI are not selected.
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* These outputs are available on J1, pins 18 and 20, respectively.
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*
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* PE31 can be used if the ISI is not selected
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* (and the HDMI is not being used).
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* That signal is available at J3 pin 20.
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*
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* If the GMAC is not selected, then PB4 and PB5 could also be used.
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* However, these pins are not available at the I/O expansion connectors.
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*/
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#if !defined(CONFIG_SAMA5_LCDC) && !defined(CONFIG_SAMA5_ISI)
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# define PIO_PWM1_H PIO_PWM1_H_2
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#elif !defined(CONFIG_SAMA5_GMAC)
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# define PIO_PWM1_H PIO_PWM1_H_1
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#endif
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#if !defined(CONFIG_SAMA5_LCDC) && !defined(CONFIG_SAMA5_ISI)
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# define PIO_PWM1_L PIO_PWM1_L_3
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#elif !defined(CONFIG_SAMA5_ISI)
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# define PIO_PWM1_L PIO_PWM1_L_2
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#elif !defined(CONFIG_SAMA5_GMAC)
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# define PIO_PWM1_L PIO_PWM1_L_1
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#endif
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/* PWM channel 2:
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*
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* None of the output pin options are available at any of the I/O expansion
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* connectors for PWM channel 2
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*/
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#if !defined(CONFIG_SAMA5_HSMCI0)
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# define PIO_PWM2_H PIO_PWM2_H_1
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# define PIO_PWM2_L PIO_PWM2_L_1
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#elif !defined(CONFIG_SAMA5_GMAC)
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# define PIO_PWM2_H PIO_PWM2_H_2
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# define PIO_PWM2_L PIO_PWM2_L_2
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#endif
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/* PWM channel 3:
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*
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* If the GMAC is not selected, then PB12 can used and is available at
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* J3 pin 7.
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* None of the other output pins are accessible at the I/O expansion
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* connectors.
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*/
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#if !defined(CONFIG_SAMA5_GMAC)
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# define PIO_PWM3_H PIO_PWM3_H_2
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# define PIO_PWM3_L PIO_PWM3_L_2
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#elif !defined(CONFIG_SAMA5_HSMCI0)
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# define PIO_PWM3_H PIO_PWM3_H_1
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# define PIO_PWM3_L PIO_PWM3_L_1
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#endif
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/****************************************************************************
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* Assembly Language Macros
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****************************************************************************/
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#ifdef __ASSEMBLY__
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.macro config_sdram
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.endm
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#endif /* __ASSEMBLY__ */
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#endif /* __BOARDS_ARM_SAMA5_SAMA5D3X_EK_INCLUDE_BOARD_H */
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