6fd4caf00f
Squashed commit of the following:
arch/arm/src/stm32/stm32f10xxf30xx_flash.c: Re-implemented Dmitriy Linikov's change to support multi-banked FLASH on the STM32 F1 parts AFTER separating the FLASH support by architecture and implementing more standard base+offset register addressing. Now the change goes in rather cleanly.
arch/arm/src/stm32/stm32f10xxf30xx_flash.c: Use base + offset address to simplify implementation of dual bank flash.
389 lines
9.1 KiB
C
389 lines
9.1 KiB
C
/************************************************************************************
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* arch/arm/src/stm32/stm3210xxf30xx_flash.c
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*
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* Copyright (C) 2011 Uros Platise. All rights reserved.
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* Author: Uros Platise <uros.platise@isotel.eu>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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/* Provides standard flash access functions, to be used by the flash mtd driver.
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* The interface is defined in the include/nuttx/progmem.h
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*
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* Requirements during write/erase operations on FLASH:
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* - HSI must be ON.
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* - Low Power Modes are not permitted during write/erase
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*/
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/arch.h>
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#include <stdbool.h>
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#include <semaphore.h>
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#include <assert.h>
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#include <errno.h>
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#include "stm32_flash.h"
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#include "stm32_rcc.h"
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#include "stm32_waste.h"
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#include "up_arch.h"
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/* Only for the STM32F[1|3]0xx family. */
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#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX)
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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#define FLASH_KEY1 0x45670123
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#define FLASH_KEY2 0xcdef89ab
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#define FLASH_OPTKEY1 0x08192a3b
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#define FLASH_OPTKEY2 0x4c5d6e7f
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#define FLASH_ERASEDVALUE 0xff
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#if !defined(STM32_FLASH_DUAL_BANK)
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# define STM32_FLASH_BANK0_NPAGES STM32_FLASH_NPAGES
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# define STM32_FLASH_BANK0_BASE STM32_FLASH_BASE
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#endif
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/************************************************************************************
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* Private Data
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************************************************************************************/
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static sem_t g_sem = SEM_INITIALIZER(1);
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/************************************************************************************
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* Private Functions
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************************************************************************************/
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static void sem_lock(void)
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{
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int ret;
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do
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{
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/* Take the semaphore (perhaps waiting) */
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ret = nxsem_wait(&g_sem);
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/* The only case that an error should occur here is if the wait was
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* awakened by a signal.
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*/
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DEBUGASSERT(ret == OK || ret == -EINTR);
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}
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while (ret == -EINTR);
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}
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static inline void sem_unlock(void)
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{
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nxsem_post(&g_sem);
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}
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static void flash_unlock(uintptr_t base)
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{
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while ((getreg32(base + STM32_FLASH_SR_OFFSET) & FLASH_SR_BSY) != 0)
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{
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up_waste();
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}
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if ((getreg32(base + STM32_FLASH_CR_OFFSET) & FLASH_CR_LOCK) != 0)
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{
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/* Unlock sequence */
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putreg32(FLASH_KEY1, base + STM32_FLASH_KEYR_OFFSET);
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putreg32(FLASH_KEY2, base + STM32_FLASH_KEYR_OFFSET);
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}
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}
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static void flash_lock(uintptr_t base)
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{
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modifyreg32(base + STM32_FLASH_CR_OFFSET, 0, FLASH_CR_LOCK);
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}
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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void stm32_flash_unlock(void)
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{
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sem_lock();
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flash_unlock(STM32_FLASH_BANK0_BASE);
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#if defined(STM32_FLASH_DUAL_BANK)
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flash_unlock(STM32_FLASH_BANK1_BASE);
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#endif
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sem_unlock();
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}
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void stm32_flash_lock(void)
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{
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sem_lock();
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flash_lock(STM32_FLASH_BANK0_BASE);
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#if defined(STM32_FLASH_DUAL_BANK)
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flash_lock(STM32_FLASH_BANK1_BASE);
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#endif
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sem_unlock();
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}
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size_t up_progmem_pagesize(size_t page)
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{
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return STM32_FLASH_PAGESIZE;
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}
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size_t up_progmem_erasesize(size_t page)
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{
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return STM32_FLASH_PAGESIZE;
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}
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ssize_t up_progmem_getpage(size_t addr)
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{
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if (addr >= STM32_FLASH_BASE)
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{
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addr -= STM32_FLASH_BASE;
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}
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if (addr >= STM32_FLASH_SIZE)
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{
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return -EFAULT;
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}
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return addr / STM32_FLASH_PAGESIZE;
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}
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size_t up_progmem_getaddress(size_t page)
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{
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if (page >= STM32_FLASH_NPAGES)
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{
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return SIZE_MAX;
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}
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return page * STM32_FLASH_PAGESIZE + STM32_FLASH_BASE;
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}
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size_t up_progmem_npages(void)
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{
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return STM32_FLASH_NPAGES;
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}
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bool up_progmem_isuniform(void)
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{
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#ifdef STM32_FLASH_PAGESIZE
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return true;
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#else
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return false;
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#endif
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}
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ssize_t up_progmem_ispageerased(size_t page)
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{
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size_t addr;
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size_t count;
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size_t bwritten = 0;
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if (page >= STM32_FLASH_NPAGES)
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{
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return -EFAULT;
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}
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/* Verify */
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for (addr = up_progmem_getaddress(page), count = up_progmem_pagesize(page);
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count; count--, addr++)
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{
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if (getreg8(addr) != FLASH_ERASEDVALUE)
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{
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bwritten++;
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}
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}
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return bwritten;
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}
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ssize_t up_progmem_erasepage(size_t page)
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{
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uintptr_t base;
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size_t page_address;
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if (page >= STM32_FLASH_NPAGES)
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{
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return -EFAULT;
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}
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#if defined(STM32_FLASH_DUAL_BANK)
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/* Handle paged FLASH */
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if (page >= STM32_FLASH_BANK0_NPAGES)
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{
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base = STM32_FLASH_BANK1_BASE;
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}
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else
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{
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base = STM32_FLASH_BANK0_BASE;
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}
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#else
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base = STM32_FLASH_BANK0_BASE;
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#endif
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sem_lock();
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if ((getreg32(base + STM32_RCC_CR_OFFSET) & RCC_CR_HSION) == 0)
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{
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sem_unlock();
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return -EPERM;
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}
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/* Get flash ready and begin erasing single page */
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flash_unlock(base);
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modifyreg32(base + STM32_FLASH_CR_OFFSET, 0, FLASH_CR_PER);
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/* Must be valid - page index checked above */
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page_address = up_progmem_getaddress(page);
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putreg32(page_address, base + STM32_FLASH_AR_OFFSET);
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modifyreg32(base + STM32_FLASH_CR_OFFSET, 0, FLASH_CR_STRT);
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while ((getreg32(base + STM32_FLASH_SR_OFFSET) & FLASH_SR_BSY) != 0)
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{
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up_waste();
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}
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modifyreg32(base + STM32_FLASH_CR_OFFSET, FLASH_CR_PER, 0);
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sem_unlock();
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/* Verify */
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if (up_progmem_ispageerased(page) == 0)
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{
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return up_progmem_pagesize(page); /* success */
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}
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else
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{
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return -EIO; /* failure */
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}
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}
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ssize_t up_progmem_write(size_t addr, const void *buf, size_t count)
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{
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uintptr_t base;
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uint16_t *hword = (uint16_t *)buf;
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size_t written = count;
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#if defined(STM32_FLASH_DUAL_BANK)
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/* Handle paged FLASH */
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if (page >= STM32_FLASH_BANK0_NPAGES)
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{
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base = STM32_FLASH_BANK1_BASE;
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}
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else
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{
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base = STM32_FLASH_BANK0_BASE;
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}
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#else
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base = STM32_FLASH_BANK0_BASE;
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#endif
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/* STM32 requires half-word access */
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if (count & 1)
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{
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return -EINVAL;
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}
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/* Check for valid address range */
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if (addr >= STM32_FLASH_BASE)
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{
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addr -= STM32_FLASH_BASE;
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}
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if ((addr+count) > STM32_FLASH_SIZE)
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{
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return -EFAULT;
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}
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sem_lock();
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if ((getreg32(base + STM32_RCC_CR_OFFSET) & RCC_CR_HSION) == 0)
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{
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sem_unlock();
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return -EPERM;
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}
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/* Get flash ready and begin flashing */
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flash_unlock(base);
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modifyreg32(base + STM32_FLASH_CR_OFFSET, 0, FLASH_CR_PG);
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for (addr += STM32_FLASH_BASE; count; count -= 2, hword++, addr += 2)
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{
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/* Write half-word and wait to complete */
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putreg16(*hword, addr);
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while ((getreg32(base + STM32_FLASH_SR_OFFSET) & FLASH_SR_BSY) != 0)
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{
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up_waste();
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}
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/* Verify */
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if ((getreg32(base + STM32_FLASH_SR_OFFSET) & FLASH_SR_WRPRT_ERR) != 0)
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{
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modifyreg32(base + STM32_FLASH_CR_OFFSET, FLASH_CR_PG, 0);
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sem_unlock();
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return -EROFS;
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}
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if (getreg16(addr) != *hword)
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{
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modifyreg32(base + STM32_FLASH_CR_OFFSET, FLASH_CR_PG, 0);
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sem_unlock();
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return -EIO;
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}
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}
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modifyreg32(base + STM32_FLASH_CR_OFFSET, FLASH_CR_PG, 0);
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sem_unlock();
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return written;
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}
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#endif /* defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) */
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