121 lines
5.3 KiB
C
121 lines
5.3 KiB
C
/*****************************************************************************
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* arch/arm/include/imxrt/chip.h
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Authors: Gregory Nutt <gnutt@nuttx.org>
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* David Sidrane <david_s5@nscdg.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*****************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_IMXRT_CHIP_H
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#define __ARCH_ARM_INCLUDE_IMXRT_CHIP_H
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/*****************************************************************************
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* Included Files
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*****************************************************************************/
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#include <nuttx/config.h>
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/*****************************************************************************
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* Pre-processor Definitions
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*****************************************************************************/
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/* Get customizations for each supported chip */
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#if defined(CONFIG_ARCH_CHIP_MIMXRT1021CAG4A) || \
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defined(CONFIG_ARCH_CHIP_MIMXRT1021CAF4A) || \
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defined(CONFIG_ARCH_CHIP_MIMXRT1021DAF5A) || \
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defined(CONFIG_ARCH_CHIP_MIMXRT1021DAG5A)
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/* MIMXRT1021CAG4A - 144 pin, 400MHz Industrial
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* MIMXRT1021CAF4A - 100 pin, 400MHz Industrial
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* MIMXRT1021DAF5A - 100 pin, 500MHz Consumer
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* MIMXRT1021DAG5A - 144 pin, 500MHz Consumer
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*/
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# define IMXRT_OCRAM_SIZE (256 * 1024) /* 256Kb OCRAM */
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# define IMXRT_GPIO_NPORTS 5 /* Five total ports */
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/* but 4 doesn't exist */
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#elif defined(CONFIG_ARCH_CHIP_MIMXRT1051DVL6A) || \
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defined(CONFIG_ARCH_CHIP_MIMXRT1051CVL5A) || \
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defined(CONFIG_ARCH_CHIP_MIMXRT1052DVL6A) || \
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defined(CONFIG_ARCH_CHIP_MIMXRT1052CVL5A)
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/* MIMXRT1051CVL5A - Industrial, Reduced Features, 528MHz
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* MIMXRT1051DVL6A - Consumer, Reduced Features, 600MHz
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* MIMXRT1052CVL5A - Industrial, Full Feature, 528MHz
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* MIMXRT1052DVL6A - Consumer, Full Feature, 600MHz
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*/
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# define IMXRT_OCRAM_SIZE (512 * 1024) /* 512Kb OCRAM */
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# define IMXRT_GPIO_NPORTS 5 /* Five total ports */
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#elif defined(CONFIG_ARCH_CHIP_MIMXRT1061DVL6A) || \
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defined(CONFIG_ARCH_CHIP_MIMXRT1061CVL5A) || \
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defined(CONFIG_ARCH_CHIP_MIMXRT1062DVL6A) || \
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defined(CONFIG_ARCH_CHIP_MIMXRT1062CVL5A)
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/* MIMXRT1061CVL5A - Industrial, Reduced Features, 528MHz
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* MIMXRT1061DVL6A - Consumer, Reduced Features, 600MHz
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* MIMXRT1062CVL5A - Industrial, Full Feature, 528MHz
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* MIMXRT1062DVL6A - Consumer, Full Feature, 600MHz
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*/
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# define IMXRT_OCRAM_SIZE (1024 * 1024) /* 1024Kb OCRAM */
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# define IMXRT_GPIO_NPORTS 9 /* Nine total ports */
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#else
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# error "Unknown i.MX RT chip type"
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#endif
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/* NVIC priority levels ******************************************************
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/* Each priority field holds an 8-bit priority value, 0-15. The lower the
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* value, the greater the priority of the corresponding interrupt. The i.MX
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* RT processor implements only bits[7:4] of each field, bits[3:0] read as
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* zero and ignore writes.
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*/
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#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits[7:4] set is min pri */
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#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
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#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
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#define NVIC_SYSH_PRIORITY_STEP 0x40 /* Two bits of interrupt pri used */
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/*****************************************************************************
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* Public Types
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*****************************************************************************/
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/*****************************************************************************
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* Public Data
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*****************************************************************************/
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/*****************************************************************************
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* Public Functions
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*****************************************************************************/
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#endif /* __ARCH_ARM_INCLUDE_IMXRT_CHIP_H */
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