338 lines
11 KiB
C
338 lines
11 KiB
C
/****************************************************************************
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* configs/olimex-lpc-h3131/src/lp31_mem.c
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*
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Based on the EA3131 SDRAM initialization logic with adjustments to the
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* timing parameters taken from Olimex LPC-H3131 sample code.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <debug.h>
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#include <nuttx/arch.h>
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#include <arch/board/board.h>
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#include "chip.h"
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#include "up_arch.h"
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#include "lpc31_syscreg.h"
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#include "lpc31_cgudrvr.h"
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#include "lpc31_mpmc.h"
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#include "lpc_h3131.h"
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#ifdef CONFIG_LPC31_EXTDRAM
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* My LPC-H3131 is fitted with a Samsung K4S561632J-UC/L75 256Mbit DRAM.
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* The FLASH organization is 16Mbit x 16
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*/
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/* Command, address, and data delay (DEL2) */
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#define H3131_MPMC_DELAY ((0x00 << SYSCREG_MPMC_DELAYMODES_DEL1_SHIFT) | \
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(0x20 << SYSCREG_MPMC_DELAYMODES_DEL2_SHIFT) | \
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(0x24 << SYSCREG_MPMC_DELAYMODES_DEL3_SHIFT))
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/* Delay constants in nanosecondss for K4S561632J-UC/L75 SDRAM on board */
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/* 90MHz SDRAM Clock */
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#define H3131_SDRAM_REFRESH (15625)
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#define H3131_SDRAM_TRP (20) /* ns */
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#define H3131_SDRAM_TRAS (48) /* ns */
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#define H3131_SDRAM_TAPR (2) /* clocks */
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#define H3131_SDRAM_TWR (15) /* ns */
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#define H3131_SDRAM_TRC (72) /* ns */
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#define H3131_SDRAM_TRFC (80) /* ns */
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#define H3131_SDRAM_TREX (80) /* ns */
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#define H3131_SDRAM_TXSR (80) /* ns */
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#define H3131_SDRAM_TDAL (5) /* clocks */
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#define H3131_SDRAM_TRRD (2) /* clocks */
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#define H3131_SDRAM_TMRD (2) /* clocks */
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: lpc31_ns2clk
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*
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* Description:
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* Convert nanoseconds to units of HCLK clocks
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*
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****************************************************************************/
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static uint32_t lpc31_ns2clk(uint32_t ns, uint32_t hclk2)
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{
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/* delay (ns) * hclk (Hz) / scale (ns/sec) = cycles
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*
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* Example: ns=80, hclk2=90000000
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* clocks = 80 * 90000000 / 1000000000 + 1 = 8 (actual 7.2 cycles)
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*/
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uint64_t tmp = (uint64_t)ns * (uint64_t)hclk2 / 1000000000ull;
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if (tmp > 0)
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{
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tmp++;
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}
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return (uint32_t)tmp;
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}
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/****************************************************************************
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* Name: lpc31_sdraminitialize
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*
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* Description:
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* Configure SDRAM on the Olimex LPC-H3131 board
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*
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* My LPC-H3131 is fitted with a Samsung K4S561632J-UC/L75 256Mbit DRAM.
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* The FLASH organization is 16Mbit x 16
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*
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****************************************************************************/
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static inline void lpc31_sdraminitialize(void)
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{
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uint32_t regval;
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/* These run-time calculations can be reduced dramatically if hclk is
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* replaced with an apriori value.
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*/
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#ifdef CONFIG_LPC31_SDRAMHCLK
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# define HCLK CONFIG_LPC31_SDRAMHCLK
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#else
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uint32_t hclk = lpc31_clkfreq(CLKID_MPMCCFGCLK2, DOMAINID_SYS);
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# define HCLK hclk
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#endif
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/* Check RTL for divide by 2 possible. If so change then enable the following logic */
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#if 0
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uint32_t hclk2 = hclk;
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if (((getreg32(LPC31_MPMC_CONFIG) & MPMC_CONFIG_CLK)) != 0)
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{
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hclk2 >>= 1;
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}
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# define HCLK2 hclk2
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#else
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# define HCLK2 hclk
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#endif
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up_udelay(100);
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/* Set command delay strategy */
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putreg32(MPMC_DYNREADCONFIG_CMDDEL, LPC31_MPMC_DYNREADCONFIG);
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/* Configure device config register nSDCE0 for proper width SDRAM:
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* Type: 256Mb (16Mx16), 4 banks, row length=13, column length=9
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* Buffer disabled, writes not protected.
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*/
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putreg32((MPMC_DYNCONFIG0_MDSDRAM | MPMC_DYNCONFIG_HP16_16MX16),
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LPC31_MPMC_DYNCONFIG0);
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/* Disable buffers + writes not protected */
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regval = getreg32(LPC31_MPMC_DYNCONFIG0);
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regval &= ~(MPMC_DYNCONFIG0_B | MPMC_DYNCONFIG0_P);
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putreg32(regval, LPC31_MPMC_DYNCONFIG0);
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/* Set RAS/CAS delays*/
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putreg32((MPMC_DYNRASCAS0_RAS2CLK | MPMC_DYNRASCAS0_CAS2CLK),
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LPC31_MPMC_DYNRASCAS0);
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/* Configure SDRAM timing */
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putreg32(lpc31_ns2clk(H3131_SDRAM_TRP, HCLK2), LPC31_MPMC_DYNTRP);
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putreg32(lpc31_ns2clk(H3131_SDRAM_TRAS, HCLK2), LPC31_MPMC_DYNTRAS);
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putreg32(lpc31_ns2clk(H3131_SDRAM_TREX, HCLK2), LPC31_MPMC_DYNTSREX);
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putreg32(H3131_SDRAM_TAPR, LPC31_MPMC_DYNTAPR);
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putreg32(H3131_SDRAM_TDAL + lpc31_ns2clk(H3131_SDRAM_TRP, HCLK2),
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LPC31_MPMC_DYNTDAL);
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putreg32(lpc31_ns2clk(H3131_SDRAM_TWR, HCLK2), LPC31_MPMC_DYNTWR);
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putreg32(lpc31_ns2clk(H3131_SDRAM_TRC, HCLK2), LPC31_MPMC_DYNTRC);
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putreg32(lpc31_ns2clk(H3131_SDRAM_TRFC, HCLK2), LPC31_MPMC_DYNTRFC);
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putreg32(lpc31_ns2clk(H3131_SDRAM_TXSR, HCLK2), LPC31_MPMC_DYNTXSR);
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putreg32(H3131_SDRAM_TRRD, LPC31_MPMC_DYNTRRD);
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putreg32(H3131_SDRAM_TMRD, LPC31_MPMC_DYNTMRD);
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/* JEDEC General SDRAM Initialization Sequence DELAY to allow power and
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* clocks to stabilize ~100 us NOP
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*/
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up_udelay(100);
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/* Issue continuous NOP commands */
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putreg32((MPMC_DYNCONTROL_CE|MPMC_DYNCONTROL_CS|MPMC_DYNCONTROL_INOP),
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LPC31_MPMC_DYNCONTROL);
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/* Wait ~200us */
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up_udelay(200);
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/* Issue a "pre-charge all" command */
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putreg32((MPMC_DYNCONTROL_CE|MPMC_DYNCONTROL_CS|MPMC_DYNCONTROL_IPALL),
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LPC31_MPMC_DYNCONTROL);
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/* Minimum refresh pulse interval (tRFC) for MT48LC32M16A2=80nsec,
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* 100nsec provides more than adequate interval.
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*/
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putreg32(1, LPC31_MPMC_DYNREFRESH);
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/* Wait ~250us */
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up_udelay(250);
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/* Recommended refresh interval for normal operation of the Micron
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* MT48LC16LFFG = 7.8125usec (128KHz rate). ((HCLK / 128000) - 1) =
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* refresh counter interval rate, (subtract one for safety margin).
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*
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* REVISIT: Is this okay for the Samsung part?
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*/
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putreg32(lpc31_ns2clk(H3131_SDRAM_REFRESH, HCLK) >> 4,
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LPC31_MPMC_DYNREFRESH);
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/* Select mode register update mode */
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putreg32((MPMC_DYNCONTROL_CE|MPMC_DYNCONTROL_CS|MPMC_DYNCONTROL_IMODE),
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LPC31_MPMC_DYNCONTROL);
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/* Program the SDRAM internal mode registers on bank nSDCE0 and reconfigure
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* the SDRAM chips. Bus speeds up to 90MHz requires use of a CAS latency = 2.
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* To get correct value on address bus CAS cycle, requires a shift by 12 for
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* 16bit mode
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*/
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(void)getreg32(LPC31_EXTSDRAM0_VSECTION | (0x23 << 12));
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/* Select normal operating mode */
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putreg32(MPMC_DYNCONTROL_INORMAL, LPC31_MPMC_DYNCONTROL);
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/* Enable buffers */
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regval = getreg32(LPC31_MPMC_DYNCONFIG0);
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regval |= MPMC_DYNCONFIG0_B;
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putreg32(regval, LPC31_MPMC_DYNCONFIG0);
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: lpc31_meminitialize
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*
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* Description:
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* Initialize external memory resources (sram, sdram, nand, nor, etc.)
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*
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****************************************************************************/
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void lpc31_meminitialize(void)
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{
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/* Configure the LCD pins in external bus interface (EBI/MPMC) memory mode.
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*
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* LCD_CSB -> MPMC_NSTCS_0
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* LCD_DB_1 -> MPMC_NSTCS_1
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* LCD_DB_0 -> MPMC_CLKOUT
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* LCD_E_RD -> MPMC_CKE
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* LCD_RS -> MPMC_NDYCS
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* LCD_RW_WR -> MPMC_DQM_1
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* LCD_DB_2 -> EBI_A_2
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* LCD_DB_3 -> EBI_A_3 l
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* LCD_DB_4 -> EBI_A_4 l
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* LCD_DB_5 -> EBI_A_5 l
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* LCD_DB_6 -> EBI_A_6
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* LCD_DB_7 -> EBI_A_7
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* LCD_DB_8 -> EBI_A_8
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* LCD_DB_9 -> EBI_A_9
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* LCD_DB_10 -> EBI_A_10
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* LCD_DB_11 -> EBI_A_11
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* LCD_DB_12 -> EBI_A_12
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* LCD_DB_13 -> EBI_A_13
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* LCD_DB_14 -> EBI_A_14
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* LCD_DB_15 -> EBI_A_15
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*/
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putreg32(SYSCREG_MUX_LCDEBISEL_EBIMPMC, LPC31_SYSCREG_MUX_LCDEBISEL);
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/* Enable EBI clock */
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lpc31_enableclock(CLKID_EBICLK);
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/* Enable MPMC controller clocks */
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lpc31_enableclock(CLKID_MPMCCFGCLK);
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lpc31_enableclock(CLKID_MPMCCFGCLK2);
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lpc31_enableclock(CLKID_MPMCCFGCLK3);
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/* Enable the external memory controller */
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putreg32(MPMC_CONTROL_E, LPC31_MPMC_CONTROL);
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/* Force HCLK to MPMC_CLK to 1:1 ratio, little-endian mode */
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putreg32(0, LPC31_MPMC_CONFIG);
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/* Set MPMC delay based on trace lengths between SDRAM and the chip
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* and on the delay strategy used for SDRAM.
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*/
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putreg32(H3131_MPMC_DELAY, LPC31_SYSCREG_MPMC_DELAYMODES);
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/* Configure Samsung K4S561632J-UC/L75 DRAM on the H3131 board */
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lpc31_sdraminitialize();
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}
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#endif /* CONFIG_LPC31_EXTDRAM */
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