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nuttx/arch/arm/include/stm32h7/chip.h
Nathan Hartman 9b9d1fc7ca arch/stm32h7: Extend support to all STM32H7x3xx 
All parts in the STM32H7x3xx family have the same pinmap, etc.,
so extending support to all members of the family required only
minimal changes: Adding them to Kconfig, extending some
preprocessor logic, and minor code changes.

arch/arm/src/stm32h7/Kconfig:

    * Add explicit support for all microcontrollers in the
      STM32H7x3xx family by adding support for:
        - STM32H743AG
        - STM32H743AI
        - STM32H743BG
        - STM32H743BI
        - STM32H743IG
        - STM32H743II
        - STM32H743VG
        - STM32H743VI
        - STM32H743XG
        - STM32H743XI
        - STM32H743ZG
        - STM32H753AI
        - STM32H753BI
        - STM32H753VI
        - STM32H753XI
        - STM32H753ZI

    * Fix TODO items for IO_CONFIG (all STM32H7X3XX).

    * Because 100-pin parts lack GPIO ports F and G, but have
      port H, create the new hidden configs STM32H7_HAVE_GPIOF
      and STM32H7_HAVE_GPIOG.

    * STM32H7_STM32H7X3XX:
      - Select STM32H7_HAVE_GPIOF and STM32H7_HAVE_GPIOG only
        when not STM32H7_IO_CONFIG_V (100-pin part).
      - STM32H7_STM32H7X3XX: select STM32H7_HAVE_SPI5 for all
        IO configs except V (100-pin part), which doesn't expose
        SPI5 due to pin count.

    * STM32H7_STM32H7X7XX: Always select STM32H7_HAVE_GPIOF and
      STM32H7_HAVE_GPIOG because we aren't adding more part
      numbers in this family.

    * Remove extraneous (duplicate) "bool" and "default n"
      lines.

    * config STM32H7_FMC: Fix indent (contents were indented
      with spaces while rest of file uses tabs).

arch/arm/include/stm32h7/chip.h:

    * Extend preprocessor logic to add support for the new
      MCU part numbers.

    * Expand table of differences between family members.

    * Define STM32H7_NGPIO based on IO_CONFIGs decided in Kconfig.

    * If IO config is not known, issue compile-time #error
      with grep-friendly "CONFIG_STM32H7_IO_CONFIG_x Not Set."
      Suggested by davids5.

arch/arm/src/stm32h7/hardware/stm32h7x3xx_gpio.h:
arch/arm/src/stm32h7/stm32h7x3xx_rcc.c:
arch/arm/src/stm32h7/stm32h7x7xx_rcc.c:

    * When checking STM32H7_NGPIO > 5 or 6, check also
      CONFIG_STM32H7_HAVE_GPIOF or CONFIG_STM32H7_HAVE_GPIOG.

arch/arm/src/stm32h7/stm32_gpio.c:

    * stm32_configgpio(): When applicable, make sure we're not
      trying to configure one of the missing ports.

    * Fix nxstyle complains (wrong end of line comment position
      and several long lines). No functional changes.

    * g_gpiobase[]: Init base address for ports F and G according to
      CONFIG_STM32H7_HAVE_GPIOF and CONFIG_STM32H7_HAVE_GPIOG.

    * stm32_configgpio(): Replace complicated check with g_gpiobase[]
      null check. Suggested by davids5.

    * stm32_gpiowrite() and stm32_gpioread(): Add previously missing
      null check of g_gpiobase[].

arch/arm/src/stm32h7/stm32_gpio.h:

    * Wrap the defines GPIO_PORTA, GPIO_PORTB, GPIO_PORTC, GPIO_PORTD,
      GPIO_PORTE, GPIO_PORTF, GPIO_PORTG, GPIO_PORTH, GPIO_PORTI,
      GPIO_PORTJ, and GPIO_PORTK in conditional logic so that the
      compiler will prevent use of ports that do not exist on the
      target MCU.

    * Fix nxstyle complaints.

Documentation/NuttX.html:

    * Remove copy-and-pasted anchor for stm32f76xx77xx.

    * Correct link to README.txt for Nucleo-H743ZI board,
      formerly on BitBucket, now on GitHub.

    * Add list item for STMicro STM32H747I-DISCO board.

Co-Authored-By: David Sidrane <David.Sidrane@Nscdg.com>
2020-04-16 13:23:12 -06:00

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/************************************************************************************
* arch/arm/include/stm32h7/chip.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* Simon Laube <simon@leitwert.ch>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_STM32H7_CHIP_H
#define __ARCH_ARM_INCLUDE_STM32H7_CHIP_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* STM32H7x3xx Differences between family members:
*
* ----------- ---------------- ----- ----
* SPI
* PART PACKAGE GPIOs I2S
* ----------- ---------------- ----- ----
* STM32H7x3Ax UFBGA169 132 6/3
* STM32H7x3Bx LQFP208 168 6/3
* STM32H7x3Ix LQFP176/UFBGA176 140 6/3
* STM32H7x3Vx LQFP100/TFBGA100 82 5/3
* STM32H7x3Xx TFBGA240 168 6/3
* STM32H7x3Zx LQFP144 114 6/3
* ----------- ---------------- ----- ----
*
* Parts STM32H7xxxG have 1024Kb of FLASH
*
* Parts STM32H7xxxI have 2048Kb of FLASH
*
* The correct FLASH size will be set CONFIG_STM32H7_FLASH_CONFIG_x or overridden
* with CONFIG_STM32H7_FLASH_OVERRIDE_x
*/
#if defined (CONFIG_ARCH_CHIP_STM32H743AG) || \
defined (CONFIG_ARCH_CHIP_STM32H743AI) || \
defined (CONFIG_ARCH_CHIP_STM32H743BG) || \
defined (CONFIG_ARCH_CHIP_STM32H743BI) || \
defined (CONFIG_ARCH_CHIP_STM32H743IG) || \
defined (CONFIG_ARCH_CHIP_STM32H743II) || \
defined (CONFIG_ARCH_CHIP_STM32H743VG) || \
defined (CONFIG_ARCH_CHIP_STM32H743VI) || \
defined (CONFIG_ARCH_CHIP_STM32H743XG) || \
defined (CONFIG_ARCH_CHIP_STM32H743XI) || \
defined (CONFIG_ARCH_CHIP_STM32H743ZG) || \
defined (CONFIG_ARCH_CHIP_STM32H743ZI) || \
defined (CONFIG_ARCH_CHIP_STM32H753AI) || \
defined (CONFIG_ARCH_CHIP_STM32H753BI) || \
defined (CONFIG_ARCH_CHIP_STM32H753II) || \
defined (CONFIG_ARCH_CHIP_STM32H753VI) || \
defined (CONFIG_ARCH_CHIP_STM32H753XI) || \
defined (CONFIG_ARCH_CHIP_STM32H753ZI)
#elif defined(CONFIG_ARCH_CHIP_STM32H747XI)
#else
# error STM32 H7 chip not identified
#endif
/* Size SRAM */
#if defined(CONFIG_STM32H7_STM32H7X3XX)
/* Memory */
# define STM32H7_SRAM_SIZE (512*1024) /* 512Kb SRAM on AXI bus Matrix (D1) */
# define STM32H7_SRAM1_SIZE (128*1024) /* 128Kb SRAM1 on AHB bus Matrix (D2) */
# define STM32H7_SRAM2_SIZE (128*1024) /* 128Kb SRAM2 on AHB bus Matrix (D2) */
# define STM32H7_SRAM3_SIZE (32*1024) /* 32Kb SRAM3 on AHB bus Matrix (D2) */
# define STM32H7_SRAM123_SIZE (288*1024) /* 128Kb SRAM123 on AHB bus Matrix (D2) */
# define STM32H7_SRAM4_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix (D3) */
# if defined(CONFIG_ARMV7M_HAVE_DTCM)
# define STM32H7_DTCM_SRAM_SIZE (128*1024) /* 128Kb DTCM SRAM on TCM interface */
# else
# define STM32H7_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */
# endif
# if defined(CONFIG_ARMV7M_HAVE_ITCM)
# define STM32H7_ITCM_SRAM_SIZE (64*1024) /* 64b ITCM SRAM on TCM interface */
# else
# define STM32H7_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */
# endif
/* Peripherals */
# if defined(CONFIG_STM32H7_IO_CONFIG_A)
# define STM32H7_NGPIO (10) /* GPIOA-GPIOJ */
# elif defined(CONFIG_STM32H7_IO_CONFIG_B)
# define STM32H7_NGPIO (11) /* GPIOA-GPIOK */
# elif defined(CONFIG_STM32H7_IO_CONFIG_I)
# define STM32H7_NGPIO (9) /* GPIOA-GPIOI */
# elif defined(CONFIG_STM32H7_IO_CONFIG_V)
# define STM32H7_NGPIO (8) /* GPIOA-GPIOH, missing GPIOF-GPIOG */
# elif defined(CONFIG_STM32H7_IO_CONFIG_X)
# define STM32H7_NGPIO (11) /* GPIOA-GPIOK */
# elif defined(CONFIG_STM32H7_IO_CONFIG_Z)
# define STM32H7_NGPIO (8) /* GPIOA-GPIOH */
# else
# error CONFIG_STM32H7_IO_CONFIG_x Not Set
# endif
# define STM32H7_NDMA (4) /* (4) DMA1, DMA2, BDMA and MDMA */
# define STM32H7_NADC (3) /* (3) ADC1-3*/
# define STM32H7_NDAC (2) /* (2) DAC1-2*/
# define STM32H7_NCMP (2) /* (2) ultra-low power comparators */
# define STM32H7_NPGA (2) /* (2) Operational amplifiers: OPAMP */
# define STM32H7_NDFSDM (1) /* (1) digital filters for sigma delta modulator */
# define STM32H7_NUSART (4) /* (4) USART1-3, 6 */
# define STM32H7_NSPI (6) /* (6) SPI1-6 */
# define STM32H7_NI2S (3) /* (3) I2S1-3 */
# define STM32H7_NUART (4) /* (4) UART4-5, 7-8 */
# define STM32H7_NI2C (4) /* (4) I2C1-4 */
# define STM32H7_NSAI (4) /* (4) SAI1-4*/
# define STM32H7_NCAN (2) /* (2) CAN1-2 */
# define STM32H7_NSDIO (2) /* (2) SDIO */
#elif defined(CONFIG_STM32H7_STM32H7X7XX)
/* Memory */
# define STM32H7_SRAM_SIZE (512*1024) /* 512Kb SRAM on AXI bus Matrix (D1) */
# define STM32H7_SRAM1_SIZE (128*1024) /* 128Kb SRAM1 on AHB bus Matrix (D2) */
# define STM32H7_SRAM2_SIZE (128*1024) /* 128Kb SRAM2 on AHB bus Matrix (D2) */
# define STM32H7_SRAM3_SIZE (32*1024) /* 32Kb SRAM3 on AHB bus Matrix (D2) */
# define STM32H7_SRAM123_SIZE (288*1024) /* 128Kb SRAM123 on AHB bus Matrix (D2) */
# define STM32H7_SRAM4_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix (D3) */
# if defined(CONFIG_ARMV7M_HAVE_DTCM)
# define STM32H7_DTCM_SRAM_SIZE (128*1024) /* 128Kb DTCM SRAM on TCM interface */
# else
# define STM32H7_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */
# endif
# if defined(CONFIG_ARMV7M_HAVE_ITCM)
# define STM32H7_ITCM_SRAM_SIZE (64*1024) /* 64b ITCM SRAM on TCM interface */
# else
# define STM32H7_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */
# endif
/* Peripherals */
# define STM32H7_NGPIO (11) /* GPIOA-GPIOK */
# define STM32H7_NDMA (4) /* (4) DMA1, DMA2, BDMA and MDMA */
# define STM32H7_NADC (3) /* (3) ADC1-3*/
# define STM32H7_NDAC (2) /* (2) DAC1-2*/
# define STM32H7_NCMP (2) /* (2) ultra-low power comparators */
# define STM32H7_NPGA (2) /* (2) Operational amplifiers: OPAMP */
# define STM32H7_NDFSDM (1) /* (1) digital filters for sigma delta modulator */
# define STM32H7_NUSART (4) /* (4) USART1-3, 6 */
# define STM32H7_NSPI (6) /* (6) SPI1-6 */
# define STM32H7_NI2S (3) /* (3) I2S1-3 */
# define STM32H7_NUART (4) /* (4) UART4-5, 7-8 */
# define STM32H7_NI2C (4) /* (4) I2C1-4 */
# define STM32H7_NSAI (4) /* (4) SAI1-4*/
# define STM32H7_NCAN (2) /* (2) CAN1-2 */
# define STM32H7_NSDIO (2) /* (2) SDIO */
#else
# error STM32 H7 chip Family not identified
#endif
/* TBD FPU Configuration */
#if defined(CONFIG_ARCH_HAVE_FPU)
#else
#endif
#if defined(CONFIG_ARCH_HAVE_DPFPU)
#else
#endif
/* Diversification based on Family and package */
#if defined(CONFIG_STM32H7_HAVE_ETHERNET)
# define STM32H7_NETHERNET 1 /* 100/100 Ethernet MAC */
#else
# define STM32H7_NETHERNET 0 /* No 100/100 Ethernet MAC */
#endif
#if defined(CONFIG_STM32H7_HAVE_FMC)
# define STM32H7_NFMC 1 /* Have FMC memory controller */
#else
# define STM32H7_NFMC 0 /* No FMC memory controller */
#endif
/* NVIC priority levels *************************************************************/
/* 16 Programmable interrupt levels */
#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set in minimum priority */
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */
#endif /* __ARCH_ARM_INCLUDE_STM32H7_CHIP_H */
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