730f7450b7
Squashed commit of the following:
Remove final references to CC3200 from the repository.
arch/arm/include/tiva: Remove all CC3200 support.
arch/arm/src/tiva: Remove all CC3200 support.
configs/cc3200-launchpad: Remove the board support directory.
164 lines
8.5 KiB
C
164 lines
8.5 KiB
C
/************************************************************************************
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* arch/arm/src/tiva/chip/lm3s_flash.h
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*
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* Copyright (C) 2009, 2013-2014 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_TIVA_CHIP_LM3S_FLASH_H
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#define __ARCH_ARM_SRC_TIVA_CHIP_LM3S_FLASH_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* FLASH dimensions ****************************************************************/
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#if defined(CONFIG_ARCH_CHIP_LM3S6965) || defined(CONFIG_ARCH_CHIP_LM4F120) || \
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defined(CONFIG_ARCH_CHIP_LM3S8962) || defined(CONFIG_ARCH_CHIP_LM3S9B96) || \
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defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || defined(CONFIG_ARCH_CHIP_TM4C123GH6PMI)
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/* These parts all support a 1KiB erase page size and a total FLASH memory size
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* of 256Kib or 256 pages.
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*/
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# define TIVA_FLASH_NPAGES 256
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# define TIVA_FLASH_PAGESIZE 1024
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#else
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# warning "No flash dimensions defined for selected chip."
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#endif
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#define TIVA_FLASH_SIZE (TIVA_FLASH_NPAGES * TIVA_FLASH_PAGESIZE)
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/* FLASH register offsets ***********************************************************/
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/* The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers are relative to the Flash
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* control base address of TIVA_FLASHCON_BASE.
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*/
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#define TIVA_FLASH_FMA_OFFSET 0x000 /* Flash memory address */
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#define TIVA_FLASH_FMD_OFFSET 0x004 /* Flash memory data */
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#define TIVA_FLASH_FMC_OFFSET 0x008 /* Flash memory control */
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#define TIVA_FLASH_FCRIS_OFFSET 0x00c /* Flash controller raw interrupt status */
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#define TIVA_FLASH_FCIM_OFFSET 0x010 /* Flash controller interrupt mask */
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#define TIVA_FLASH_FCMISC_OFFSET 0x014 /* Flash controller masked interrupt status and clear */
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/* The FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative to the
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* System Control base address of TIVA_SYSCON_BASE
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*/
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#define TIVA_FLASH_FMPRE_OFFSET 0x130 /* Flash memory protection read enable */
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#define TIVA_FLASH_FMPPE_OFFSET 0x134 /* Flash memory protection program enable */
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#define TIVA_FLASH_USECRL_OFFSET 0x140 /* USec Reload */
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#define TIVA_FLASH_USERDBG_OFFSET 0x1d0 /* User Debug */
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#define TIVA_FLASH_USERREG0_OFFSET 0x1e0 /* User Register 0 */
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#define TIVA_FLASH_USERREG1_OFFSET 0x1e4 /* User Register 1 */
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#define TIVA_FLASH_FMPRE0_OFFSET 0x200 /* Flash Memory Protection Read Enable 0 */
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#define TIVA_FLASH_FMPRE1_OFFSET 0x204 /* Flash Memory Protection Read Enable 1 */
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#define TIVA_FLASH_FMPRE2_OFFSET 0x208 /* Flash Memory Protection Read Enable 2 */
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#define TIVA_FLASH_FMPRE3_OFFSET 0x20c /* Flash Memory Protection Read Enable 3 */
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#define TIVA_FLASH_FMPPE0_OFFSET 0x400 /* Flash Memory Protection Program Enable 0 */
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#define TIVA_FLASH_FMPPE1_OFFSET 0x404 /* Flash Memory Protection Program Enable 1 */
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#define TIVA_FLASH_FMPPE2_OFFSET 0x408 /* Flash Memory Protection Program Enable 2 */
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#define TIVA_FLASH_FMPPE3_OFFSET 0x40c /* Flash Memory Protection Program Enable 3 */
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/* FLASH register addresses *********************************************************/
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/* The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers are relative to the Flash
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* control base address of TIVA_FLASHCON_BASE.
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*/
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#define TIVA_FLASH_FMA (TIVA_FLASHCON_BASE + TIVA_FLASH_FMA_OFFSET)
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#define TIVA_FLASH_FMD (TIVA_FLASHCON_BASE + TIVA_FLASH_FMD_OFFSET)
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#define TIVA_FLASH_FMC (TIVA_FLASHCON_BASE + TIVA_FLASH_FMC_OFFSET)
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#define TIVA_FLASH_FCRIS (TIVA_FLASHCON_BASE + TIVA_FLASH_FCRIS_OFFSET)
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#define TIVA_FLASH_FCIM (TIVA_FLASHCON_BASE + TIVA_FLASH_FCIM_OFFSET)
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#define TIVA_FLASH_FCMISC (TIVA_FLASHCON_BASE + TIVA_FLASH_FCMISC_OFFSET)
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/* The FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative to the
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* System Control base address of TIVA_SYSCON_BASE
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*/
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#define TIVA_FLASH_FMPRE (TIVA_SYSCON_BASE + TIVA_FLASH_FMPRE_OFFSET)
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#define TIVA_FLASH_FMPPE (TIVA_SYSCON_BASE + TIVA_FLASH_FMPPE_OFFSET)
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#define TIVA_FLASH_USECRL (TIVA_SYSCON_BASE + TIVA_FLASH_USECRL_OFFSET)
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#define TIVA_FLASH_USERDBG (TIVA_SYSCON_BASE + TIVA_FLASH_USERDBG_OFFSET)
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#define TIVA_FLASH_USERREG0 (TIVA_SYSCON_BASE + TIVA_FLASH_USERREG0_OFFSET)
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#define TIVA_FLASH_USERREG1 (TIVA_SYSCON_BASE + TIVA_FLASH_USERREG1_OFFSET)
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#define TIVA_FLASH_FMPRE0 (TIVA_SYSCON_BASE + TIVA_FLASH_FMPRE0_OFFSET)
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#define TIVA_FLASH_FMPRE1 (TIVA_SYSCON_BASE + TIVA_FLASH_FMPRE1_OFFSET)
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#define TIVA_FLASH_FMPRE2 (TIVA_SYSCON_BASE + TIVA_FLASH_FMPRE2_OFFSET)
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#define TIVA_FLASH_FMPRE3 (TIVA_SYSCON_BASE + TIVA_FLASH_FMPRE3_OFFSET)
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#define TIVA_FLASH_FMPPE0 (TIVA_SYSCON_BASE + TIVA_FLASH_FMPPE0_OFFSET)
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#define TIVA_FLASH_FMPPE1 (TIVA_SYSCON_BASE + TIVA_FLASH_FMPPE1_OFFSET)
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#define TIVA_FLASH_FMPPE2 (TIVA_SYSCON_BASE + TIVA_FLASH_FMPPE2_OFFSET)
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#define TIVA_FLASH_FMPPE3 (TIVA_SYSCON_BASE + TIVA_FLASH_FMPPE3_OFFSET)
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/* FLASH register bit definitions ***************************************************/
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#define FLASH_FMA_OFFSET_SHIFT 0 /* Bits 17-0: Address Offset */
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#define FLASH_FMA_OFFSET_MASK (0x0003ffff << FLASH_FMA_OFFSET_SHIFT)
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#define FLASH_FMC_WRITE (1 << 0) /* Write a Word into Flash Memory */
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#define FLASH_FMC_ERASE (1 << 1) /* Erase a Page of Flash Memory */
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#define FLASH_FMC_MERASE (1 << 2) /* Mass Erase Flash Memory */
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#define FLASH_FMC_COMT (1 << 3) /* Commit Register Value */
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/* This field contains a write key, which is used to minimize the incidence
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* of accidental flash writes. The value 0xA442 must be written into this
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* field for a write to occur. Writes to the FMC register without this WRKEY
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* value are ignored. A read of this field returns the value 0
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*/
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#define FLASH_FMC_WRKEY_SHIFT 16 /* Bits 16-31: Flash Write Key */
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#define FLASH_FMC_WRKEY_MASK (0xffff << FLASH_FMC_WRKEY_SHIFT)
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#define FLASH_FMC_WRKEY (0xa442 << FLASH_FMC_WRKEY_SHIFT) /* Magic write key */
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/************************************************************************************
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* Public Function Prototypes
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************************************************************************************/
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#endif /* __ARCH_ARM_SRC_TIVA_CHIP_LM3S_FLASH_H */
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