6ff1648b4f
Gregory Nutt has submitted the SGA and we can migrate the licenses to Apache. Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
710 lines
19 KiB
C
710 lines
19 KiB
C
/****************************************************************************
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* arch/arm/src/stm32/stm32f30xxx_rcc.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Allow up to 100 milliseconds for the high speed clock to become ready.
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* that is a very long delay, but if the clock does not become ready we are
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* hosed anyway. Normally this is very fast, but I have seen at least one
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* board that required this long, long timeout for the HSE to be ready.
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*/
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#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC)
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/* The FLASH latency depends on the system clock.
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*
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* Calculate the wait cycles, based on STM32_SYSCLK_FREQUENCY:
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* 0WS from 0-24MHz
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* 1WS from 24-48MHz
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* 2WS from 48-72MHz
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*/
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#if (STM32_SYSCLK_FREQUENCY <= 24000000)
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# define FLASH_ACR_LATENCY_SETTING FLASH_ACR_LATENCY_0
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#elif (STM32_SYSCLK_FREQUENCY <= 48000000)
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# define FLASH_ACR_LATENCY_SETTING FLASH_ACR_LATENCY_1
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#elif (STM32_SYSCLK_FREQUENCY <= 72000000)
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# define FLASH_ACR_LATENCY_SETTING FLASH_ACR_LATENCY_2
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#else
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# error "STM32_SYSCLK_FREQUENCY is out of range!"
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#endif
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: rcc_reset
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*
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* Description:
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* Put all RCC registers in reset state
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*
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****************************************************************************/
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static inline void rcc_reset(void)
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{
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uint32_t regval;
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putreg32(0, STM32_RCC_APB2RSTR); /* Disable APB2 Peripheral Reset */
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putreg32(0, STM32_RCC_APB1RSTR); /* Disable APB1 Peripheral Reset */
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putreg32(RCC_AHBENR_FLITFEN | RCC_AHBENR_SRAMEN,
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STM32_RCC_AHBENR); /* FLITF and SRAM Clock ON */
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putreg32(0, STM32_RCC_APB2ENR); /* Disable APB2 Peripheral Clock */
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putreg32(0, STM32_RCC_APB1ENR); /* Disable APB1 Peripheral Clock */
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regval = getreg32(STM32_RCC_CR); /* Set the HSION bit */
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regval |= RCC_CR_HSION;
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putreg32(regval, STM32_RCC_CR);
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regval = getreg32(STM32_RCC_CFGR); /* Reset SW, HPRE, PPRE1, PPRE2, USBPRE, I2SSRC, and MCO bits */
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regval &= ~(RCC_CFGR_SW_MASK | RCC_CFGR_HPRE_MASK | RCC_CFGR_PPRE1_MASK |
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RCC_CFGR_PPRE2_MASK | RCC_CFGR_USBPRE | RCC_CFGR_I2SSRC |
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RCC_CFGR_MCO_MASK);
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putreg32(regval, STM32_RCC_CFGR);
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regval = getreg32(STM32_RCC_CFGR2); /* Reset PREDIV, ADC12PRE, and ADC23PRE bits */
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regval &= ~(RCC_CFGR2_PREDIV_MASK | RCC_CFGR2_ADC12PRES_MASK |
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RCC_CFGR2_ADC34PRES_MASK);
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putreg32(regval, STM32_RCC_CFGR2);
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putreg32(0, STM32_RCC_CFGR2); /* Reset fCK source for all U[S]ARTs to PCLK */
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regval = getreg32(STM32_RCC_CR); /* Reset HSEON, CSSON and PLLON bits */
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regval &= ~(RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON);
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putreg32(regval, STM32_RCC_CR);
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regval = getreg32(STM32_RCC_CR); /* Reset HSEBYP bit */
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regval &= ~RCC_CR_HSEBYP;
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putreg32(regval, STM32_RCC_CR);
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regval = getreg32(STM32_RCC_CFGR); /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
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regval &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMUL_MASK |
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RCC_CFGR_USBPRE);
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putreg32(regval, STM32_RCC_CFGR);
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putreg32(0, STM32_RCC_CIR); /* Disable all interrupts */
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}
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/****************************************************************************
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* Name: rcc_enableahb
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*
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* Description:
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* Enable selected AHB peripherals
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*
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****************************************************************************/
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static inline void rcc_enableahb(void)
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{
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uint32_t regval;
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/* Always enable FLITF clock and SRAM clock */
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regval = RCC_AHBENR_FLITFEN | RCC_AHBENR_SRAMEN;
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/* Enable GPIO PORTA, PORTB, ... PORTF */
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regval |= (RCC_AHBENR_IOPAEN | RCC_AHBENR_IOPBEN | RCC_AHBENR_IOPCEN |
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RCC_AHBENR_IOPDEN | RCC_AHBENR_IOPEEN | RCC_AHBENR_IOPFEN);
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#ifdef CONFIG_STM32_DMA1
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/* DMA 1 clock enable */
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regval |= RCC_AHBENR_DMA1EN;
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#endif
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#ifdef CONFIG_STM32_DMA2
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/* DMA 2 clock enable */
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regval |= RCC_AHBENR_DMA2EN;
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#endif
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#ifdef CONFIG_STM32_CRC
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/* CRC clock enable */
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regval |= RCC_AHBENR_CRCEN;
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#endif
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#ifdef CONFIG_STM32_TSC
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/* CRC clock enable */
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regval |= RCC_AHBENR_TSCEN;
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#endif
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#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2)
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/* ADC1/ADC2 interface clock enable */
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regval |= RCC_AHBENR_ADC12EN;
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#endif
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#if defined(CONFIG_STM32_ADC3) || defined(CONFIG_STM32_ADC4)
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/* ADC3/ADC4 interface clock enable */
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regval |= RCC_AHBENR_ADC34EN;
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#endif
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putreg32(regval, STM32_RCC_AHBENR); /* Enable peripherals */
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}
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/****************************************************************************
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* Name: rcc_enableapb1
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*
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* Description:
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* Enable selected APB1 peripherals
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*
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****************************************************************************/
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static inline void rcc_enableapb1(void)
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{
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uint32_t regval;
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#ifdef CONFIG_STM32_USB
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/* USB clock divider. This bit must be valid before enabling the USB
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* clock in the RCC_APB1ENR register. This bit can<61>t be reset if the USB
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* clock is enabled.
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*/
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regval = getreg32(STM32_RCC_CFGR);
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regval &= ~RCC_CFGR_USBPRE;
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regval |= STM32_CFGR_USBPRE;
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putreg32(regval, STM32_RCC_CFGR);
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#endif
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/* Set the appropriate bits in the APB1ENR register to enabled the
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* selected APB1 peripherals.
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*/
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regval = getreg32(STM32_RCC_APB1ENR);
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#ifdef CONFIG_STM32_TIM2
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/* Timer 2 clock enable */
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#ifdef CONFIG_STM32_FORCEPOWER
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regval |= RCC_APB1ENR_TIM2EN;
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#endif
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#endif
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#ifdef CONFIG_STM32_TIM3
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/* Timer 3 clock enable */
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#ifdef CONFIG_STM32_FORCEPOWER
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regval |= RCC_APB1ENR_TIM3EN;
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#endif
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#endif
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#ifdef CONFIG_STM32_TIM4
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/* Timer 4 clock enable */
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#ifdef CONFIG_STM32_FORCEPOWER
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regval |= RCC_APB1ENR_TIM4EN;
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#endif
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#endif
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#ifdef CONFIG_STM32_TIM6
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/* Timer 6 clock enable */
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#ifdef CONFIG_STM32_FORCEPOWER
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regval |= RCC_APB1ENR_TIM6EN;
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#endif
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#endif
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#ifdef CONFIG_STM32_TIM7
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/* Timer 7 clock enable */
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#ifdef CONFIG_STM32_FORCEPOWER
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regval |= RCC_APB1ENR_TIM7EN;
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#endif
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#endif
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#ifdef CONFIG_STM32_WWDG
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/* Window Watchdog clock enable */
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regval |= RCC_APB1ENR_WWDGEN;
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#endif
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#ifdef CONFIG_STM32_SPI2
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/* SPI 2 clock enable */
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regval |= RCC_APB1ENR_SPI2EN;
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#endif
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#ifdef CONFIG_STM32_SPI3
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/* SPI 3 clock enable */
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regval |= RCC_APB1ENR_SPI3EN;
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#endif
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#ifdef CONFIG_STM32_USART2
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/* USART 2 clock enable */
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regval |= RCC_APB1ENR_USART2EN;
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#endif
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#ifdef CONFIG_STM32_USART3
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/* USART 3 clock enable */
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regval |= RCC_APB1ENR_USART3EN;
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#endif
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#ifdef CONFIG_STM32_UART4
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/* UART 4 clock enable */
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regval |= RCC_APB1ENR_UART4EN;
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#endif
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#ifdef CONFIG_STM32_UART5
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/* UART 5 clock enable */
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regval |= RCC_APB1ENR_UART5EN;
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#endif
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#ifdef CONFIG_STM32_I2C1
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/* I2C 1 clock enable */
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#ifdef CONFIG_STM32_FORCEPOWER
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regval |= RCC_APB1ENR_I2C1EN;
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#endif
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#endif
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#ifdef CONFIG_STM32_I2C2
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/* I2C 2 clock enable */
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#ifdef CONFIG_STM32_FORCEPOWER
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regval |= RCC_APB1ENR_I2C2EN;
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#endif
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#endif
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#ifdef CONFIG_STM32_USB
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/* USB clock enable */
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regval |= RCC_APB1ENR_USBEN;
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#endif
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#ifdef CONFIG_STM32_CAN1
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/* CAN1 clock enable */
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regval |= RCC_APB1ENR_CAN1EN;
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#endif
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#ifdef CONFIG_STM32_PWR
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/* Power interface clock enable */
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regval |= RCC_APB1ENR_PWREN;
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#endif
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#ifdef CONFIG_STM32_DAC1
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/* DAC2 interface clock enable */
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regval |= RCC_APB1ENR_DAC1EN;
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#endif
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#ifdef CONFIG_STM32_DAC2
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/* DAC2 interface clock enable */
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regval |= RCC_APB1ENR_DAC2EN;
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#endif
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putreg32(regval, STM32_RCC_APB1ENR);
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}
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/****************************************************************************
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* Name: rcc_enableapb2
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*
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* Description:
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* Enable selected APB2 peripherals
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*
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****************************************************************************/
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static inline void rcc_enableapb2(void)
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{
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uint32_t regval;
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/* Set the appropriate bits in the APB2ENR register to enabled the
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* selected APB2 peripherals.
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*/
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regval = getreg32(STM32_RCC_APB2ENR);
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#ifdef CONFIG_STM32_SYSCFG
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/* SYSCFG clock */
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regval |= RCC_APB2ENR_SYSCFGEN;
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#endif
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#ifdef CONFIG_STM32_TIM1
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/* TIM1 Timer clock enable */
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#ifdef CONFIG_STM32_FORCEPOWER
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regval |= RCC_APB2ENR_TIM1EN;
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#endif
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#endif
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#ifdef CONFIG_STM32_SPI1
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/* SPI 1 clock enable */
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regval |= RCC_APB2ENR_SPI1EN;
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#endif
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#ifdef CONFIG_STM32_TIM8
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/* TIM8 Timer clock enable */
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#ifdef CONFIG_STM32_FORCEPOWER
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regval |= RCC_APB2ENR_TIM8EN;
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#endif
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#endif
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#ifdef CONFIG_STM32_USART1
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/* USART1 clock enable */
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regval |= RCC_APB2ENR_USART1EN;
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#endif
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#ifdef CONFIG_STM32_TIM15
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/* TIM15 Timer clock enable */
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#ifdef CONFIG_STM32_FORCEPOWER
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regval |= RCC_APB2ENR_TIM15EN;
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#endif
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#endif
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#ifdef CONFIG_STM32_TIM16
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/* TIM16 Timer clock enable */
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#ifdef CONFIG_STM32_FORCEPOWER
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regval |= RCC_APB2ENR_TIM16EN;
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#endif
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#endif
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#ifdef CONFIG_STM32_TIM17
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/* TIM17 Timer clock enable */
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#ifdef CONFIG_STM32_FORCEPOWER
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regval |= RCC_APB2ENR_TIM17EN;
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#endif
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#endif
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putreg32(regval, STM32_RCC_APB2ENR);
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}
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/****************************************************************************
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* Name: stm32_stdclockconfig
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*
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* Description:
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* Called to change to new clock based on settings in board.h. This
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* version is for the Connectivity Line parts.
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*
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* NOTE: This logic would need to be extended if you need to select low-
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* power clocking modes!
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****************************************************************************/
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#if !defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) && defined(CONFIG_STM32_CONNECTIVITYLINE)
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static void stm32_stdclockconfig(void)
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{
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uint32_t regval;
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/* Enable HSE */
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regval = getreg32(STM32_RCC_CR);
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regval &= ~RCC_CR_HSEBYP; /* Disable HSE clock bypass */
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regval |= RCC_CR_HSEON; /* Enable HSE */
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putreg32(regval, STM32_RCC_CR);
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/* Enable FLASH prefetch buffer and set FLASH wait states */
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regval = getreg32(STM32_FLASH_ACR);
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regval &= ~FLASH_ACR_LATENCY_MASK;
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regval |= (FLASH_ACR_LATENCY_SETTING | FLASH_ACR_PRTFBE);
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putreg32(regval, STM32_FLASH_ACR);
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/* Set up PLL input scaling (with source = PLL2) */
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regval = getreg32(STM32_RCC_CFGR2);
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regval &= ~(RCC_CFGR2_PREDIV2_MASK | RCC_CFGR2_PLL2MUL_MASK |
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RCC_CFGR2_PREDIV1SRC_MASK | RCC_CFGR2_PREDIV1_MASK);
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regval |= (STM32_PLL_PREDIV2 | STM32_PLL_PLL2MUL |
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RCC_CFGR2_PREDIV1SRC_PLL2 | STM32_PLL_PREDIV1);
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putreg32(regval, STM32_RCC_CFGR2);
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/* Set the PCLK2 divider */
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regval = getreg32(STM32_RCC_CFGR);
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regval &= ~(RCC_CFGR_PPRE2_MASK | RCC_CFGR_HPRE_MASK);
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regval |= STM32_RCC_CFGR_PPRE2;
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regval |= RCC_CFGR_HPRE_SYSCLK;
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putreg32(regval, STM32_RCC_CFGR);
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/* Set the PCLK1 divider */
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regval = getreg32(STM32_RCC_CFGR);
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regval &= ~RCC_CFGR_PPRE1_MASK;
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regval |= STM32_RCC_CFGR_PPRE1;
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putreg32(regval, STM32_RCC_CFGR);
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/* Enable PLL2 */
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regval = getreg32(STM32_RCC_CR);
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regval |= RCC_CR_PLL2ON;
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putreg32(regval, STM32_RCC_CR);
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/* Wait for PLL2 ready */
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while ((getreg32(STM32_RCC_CR) & RCC_CR_PLL2RDY) == 0);
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/* Setup PLL3 for MII/RMII clock on MCO */
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#if defined(CONFIG_STM32_MII_MCO) || defined(CONFIG_STM32_RMII_MCO)
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regval = getreg32(STM32_RCC_CFGR2);
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regval &= ~(RCC_CFGR2_PLL3MUL_MASK);
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regval |= STM32_PLL_PLL3MUL;
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putreg32(regval, STM32_RCC_CFGR2);
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/* Switch PLL3 on */
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regval = getreg32(STM32_RCC_CR);
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regval |= RCC_CR_PLL3ON;
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putreg32(regval, STM32_RCC_CR);
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while ((getreg32(STM32_RCC_CR) & RCC_CR_PLL3RDY) == 0);
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#endif
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/* Set main PLL source and multiplier */
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regval = getreg32(STM32_RCC_CFGR);
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regval &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL_MASK);
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regval |= (RCC_CFGR_PLLSRC | STM32_PLL_PLLMUL);
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putreg32(regval, STM32_RCC_CFGR);
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/* Switch main PLL on */
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regval = getreg32(STM32_RCC_CR);
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regval |= RCC_CR_PLLON;
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putreg32(regval, STM32_RCC_CR);
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while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0);
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/* Select PLL as system clock source */
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regval = getreg32(STM32_RCC_CFGR);
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regval &= ~RCC_CFGR_SW_MASK;
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regval |= RCC_CFGR_SW_PLL;
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putreg32(regval, STM32_RCC_CFGR);
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/* Wait until PLL is used as the system clock source */
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while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_PLL) == 0);
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}
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#endif
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/****************************************************************************
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* Name: stm32_stdclockconfig
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*
|
||
* Description:
|
||
* Called to change to new clock based on settings in board.h. This
|
||
* version is for the non-Connectivity Line parts.
|
||
*
|
||
* NOTE: This logic would need to be extended if you need to select low-
|
||
* power clocking modes!
|
||
****************************************************************************/
|
||
|
||
#if !defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) && \
|
||
!defined(CONFIG_STM32_CONNECTIVITYLINE)
|
||
static void stm32_stdclockconfig(void)
|
||
{
|
||
uint32_t regval;
|
||
|
||
/* If the PLL is using the HSE, or the HSE is the system clock */
|
||
|
||
#if (STM32_CFGR_PLLSRC == RCC_CFGR_PLLSRC) || (STM32_SYSCLK_SW == RCC_CFGR_SW_HSE)
|
||
{
|
||
volatile int32_t timeout;
|
||
|
||
/* Enable External High-Speed Clock (HSE) */
|
||
|
||
regval = getreg32(STM32_RCC_CR);
|
||
regval &= ~RCC_CR_HSEBYP; /* Disable HSE clock bypass */
|
||
regval |= RCC_CR_HSEON; /* Enable HSE */
|
||
putreg32(regval, STM32_RCC_CR);
|
||
|
||
/* Wait until the HSE is ready (or until a timeout elapsed) */
|
||
|
||
for (timeout = HSERDY_TIMEOUT; timeout > 0; timeout--)
|
||
{
|
||
/* Check if the HSERDY flag is the set in the CR */
|
||
|
||
if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0)
|
||
{
|
||
/* If so, then break-out with timeout > 0 */
|
||
|
||
break;
|
||
}
|
||
}
|
||
|
||
if (timeout == 0)
|
||
{
|
||
/* In the case of a timeout starting the HSE, we really don't have
|
||
* a strategy. This is almost always a hardware failure or
|
||
* misconfiguration.
|
||
*/
|
||
|
||
return;
|
||
}
|
||
}
|
||
|
||
# if defined(CONFIG_STM32_VALUELINE) && (STM32_CFGR_PLLSRC == RCC_CFGR_PLLSRC)
|
||
/* If this is a value-line part and we are using the HSE as the PLL */
|
||
|
||
# if (STM32_CFGR_PLLXTPRE >> 17) != (STM32_CFGR2_PREDIV1 & 1)
|
||
# error STM32_CFGR_PLLXTPRE must match the LSB of STM32_CFGR2_PREDIV1
|
||
# endif
|
||
|
||
/* Set the HSE prescaler */
|
||
|
||
regval = STM32_CFGR2_PREDIV1;
|
||
putreg32(regval, STM32_RCC_CFGR2);
|
||
|
||
# endif
|
||
#endif
|
||
|
||
#ifndef CONFIG_STM32_VALUELINE
|
||
/* Value-line devices don't implement flash prefetch/waitstates */
|
||
|
||
/* Enable FLASH prefetch buffer and set FLASH wait states */
|
||
|
||
regval = getreg32(STM32_FLASH_ACR);
|
||
regval &= ~FLASH_ACR_LATENCY_MASK;
|
||
regval |= (FLASH_ACR_LATENCY_SETTING | FLASH_ACR_PRTFBE);
|
||
putreg32(regval, STM32_FLASH_ACR);
|
||
#endif
|
||
|
||
/* Set the HCLK source/divider */
|
||
|
||
regval = getreg32(STM32_RCC_CFGR);
|
||
regval &= ~RCC_CFGR_HPRE_MASK;
|
||
regval |= STM32_RCC_CFGR_HPRE;
|
||
putreg32(regval, STM32_RCC_CFGR);
|
||
|
||
/* Set the PCLK2 divider */
|
||
|
||
regval = getreg32(STM32_RCC_CFGR);
|
||
regval &= ~RCC_CFGR_PPRE2_MASK;
|
||
regval |= STM32_RCC_CFGR_PPRE2;
|
||
putreg32(regval, STM32_RCC_CFGR);
|
||
|
||
/* Set the PCLK1 divider */
|
||
|
||
regval = getreg32(STM32_RCC_CFGR);
|
||
regval &= ~RCC_CFGR_PPRE1_MASK;
|
||
regval |= STM32_RCC_CFGR_PPRE1;
|
||
putreg32(regval, STM32_RCC_CFGR);
|
||
|
||
#if STM32_SYSCLK_SW == RCC_CFGR_SW_PLL
|
||
/* If we are using the PLL, configure and start it */
|
||
|
||
/* Set the PLL divider and multiplier */
|
||
|
||
regval = getreg32(STM32_RCC_CFGR);
|
||
regval &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMUL_MASK);
|
||
regval |= (STM32_CFGR_PLLSRC | STM32_CFGR_PLLXTPRE | STM32_CFGR_PLLMUL);
|
||
putreg32(regval, STM32_RCC_CFGR);
|
||
|
||
/* Enable the PLL */
|
||
|
||
regval = getreg32(STM32_RCC_CR);
|
||
regval |= RCC_CR_PLLON;
|
||
putreg32(regval, STM32_RCC_CR);
|
||
|
||
/* Wait until the PLL is ready */
|
||
|
||
while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0);
|
||
|
||
#endif
|
||
|
||
/* Select the system clock source (probably the PLL) */
|
||
|
||
regval = getreg32(STM32_RCC_CFGR);
|
||
regval &= ~RCC_CFGR_SW_MASK;
|
||
regval |= STM32_SYSCLK_SW;
|
||
putreg32(regval, STM32_RCC_CFGR);
|
||
|
||
/* Wait until the selected source is used as the system clock source */
|
||
|
||
while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != STM32_SYSCLK_SWS);
|
||
|
||
#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK)
|
||
/* Low speed internal clock source LSI
|
||
*
|
||
* TODO: There is another case where the LSI needs to
|
||
* be enabled: if the MCO pin selects LSI as source.
|
||
*/
|
||
|
||
stm32_rcc_enablelsi();
|
||
#endif
|
||
|
||
#if defined(CONFIG_STM32_RTC_LSECLOCK)
|
||
/* Normally peripheral clocks are enabled later in bootup, but we need
|
||
* clock on PWR *now* as without this setting registers that enable LSE
|
||
* won't work.
|
||
*
|
||
* NOTE: In this configuration, we can assume the CONFIG_STM32_PWR has
|
||
* been selected.
|
||
*/
|
||
|
||
regval = getreg32(STM32_RCC_APB1ENR);
|
||
regval |= RCC_APB1ENR_PWREN;
|
||
putreg32(regval, STM32_RCC_APB1ENR);
|
||
|
||
/* Low speed external clock source LSE
|
||
*
|
||
* TODO: There is another case where the LSE needs to
|
||
* be enabled: if the MCO pin selects LSE as source.
|
||
*
|
||
* TODO: There is another case where the LSE needs to
|
||
* be enabled: if USARTx selects LSE as source.
|
||
*/
|
||
|
||
stm32_rcc_enablelse();
|
||
#endif
|
||
}
|
||
#endif
|
||
|
||
/****************************************************************************
|
||
* Name: rcc_enableperiphals
|
||
****************************************************************************/
|
||
|
||
static inline void rcc_enableperipherals(void)
|
||
{
|
||
rcc_enableahb();
|
||
rcc_enableapb2();
|
||
rcc_enableapb1();
|
||
}
|
||
|
||
/****************************************************************************
|
||
* Public Functions
|
||
****************************************************************************/
|