7380b9b062
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3362 42af7a65-404d-4744-a932-0658087f49c3
452 lines
19 KiB
C
Executable File
452 lines
19 KiB
C
Executable File
/****************************************************************************
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* arch/x86/include/i486/arch.h
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*
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* Copyright (C) 2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/* This file should never be included directed but, rather,
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* only indirectly through nuttx/arch.h
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*/
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#ifndef __ARCH_X86_INCLUDE_I486_ARCH_H
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#define __ARCH_X86_INCLUDE_I486_ARCH_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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#endif
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/****************************************************************************
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* Definitions
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****************************************************************************/
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/* FLAGS bits */
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#define X86_FLAGS_CF (1 << 0) /* Bit 0: Carry Flag */
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/* Bit 1: Reserved */
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#define X86_FLAGS_PF (1 << 2) /* Bit 2: Parity Flag */
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/* Bit 3: Reserved */
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#define X86_FLAGS_AF (1 << 4) /* Bit 4: Auxillary carry Flag */
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/* Bit 5: Reserved */
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#define X86_FLAGS_ZF (1 << 6) /* Bit 6: Zero Flag */
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#define X86_FLAGS_SF (1 << 7) /* Bit 7: Sign Flag */
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#define X86_FLAGS_TF (1 << 8) /* Bit 8: Trap Flag */
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#define X86_FLAGS_IF (1 << 9) /* Bit 9: Interrupt Flag */
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#define X86_FLAGS_DF (1 << 10) /* Bit 10: Direction Flag */
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#define X86_FLAGS_OF (1 << 11) /* Bit 11: Overflow Flag */
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#define X86_FLAGS_IOPL_SHIFT (12) /* Bits 12-13: IOPL mask (286+ only)*/
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#define X86_FLAGS_IOPL_MASK (3 << X86_FLAGS_IOPL_SHIFT)
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#define X86_FLAGS_NT (1 << 14) /* Bit 14: Nested Task */
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/* Bit 15: Reserved */
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/* EFLAGS bits (Extend the basic FLAGS bit definitions) */
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#define X86_EFLAGS_RF (1 << 16) /* Bit 16: Resume Flag (386+ only) */
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#define X86_EFLAGS_VM (1 << 17) /* Bit 17: Virtual Mode (386+ only) */
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#define X86_EFLAGS_AC (1 << 18) /* Bit 18: Alignment Check (486SX+ only) */
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#define X86_EFLAGS_VIF (1 << 19) /* Bit 19: Virtual Interrupt Flag (Pentium+) */
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#define X86_EFLAGS_VIP (1 << 20) /* Bit 20: Virtual Interrupt Pending (Pentium+) */
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#define X86_EFLAGS_ID (1 << 21) /* Bit 21: CPUID detection flag (Pentium+) */
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/* Programmable Interrupt Controller (PIC) */
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/* Operational Control Words
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*
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* The first instruction the Operation Control Word 1 (OCW1) to set which
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* IRQ's to mask and which IRQ's not to.
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*/
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#define PIC1_OCW1 0x20
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#define PIC2_OCW1 0xa0
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# define PIC1_OCW1_IRQ0 (1 << 0) /* IRQ0 System Timer */
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# define PIC1_OCW1_IRQ1 (1 << 1) /* IRQ1 Keyboard */
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# define PIC1_OCW1_IRQ2 (1 << 2) /* IRQ2 PIC2 */
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# define PIC1_OCW1_IRQ3 (1 << 3) /* IRQ3 Serial Port */
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# define PIC1_OCW1_IRQ4 (1 << 4) /* IRQ4 Serial Port */
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# define PIC1_OCW1_IRQ5 (1 << 5) /* IRQ5 Reserved/Sound Card */
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# define PIC1_OCW1_IRQ6 (1 << 6) /* IRQ6 Floppy Disk Controller */
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# define PIC1_OCW1_IRQ7 (1 << 7) /* IRQ7 Parallel Port */
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# define PIC1_OCW1_ALL
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# define PIC2_OCW1_IRQ8 (1 << 0) /* IRQ8 Real Time Clock */
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# define PIC2_OCW1_IRQ9 (1 << 1) /* IRQ9 Redirected IRQ2 */
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# define PIC2_OCW1_IRQ10 (1 << 2) /* IRQ10 Reserved */
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# define PIC2_OCW1_IRQ11 (1 << 3) /* IRQ11 Reserved */
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# define PIC2_OCW1_IRQ12 (1 << 4) /* IRQ12 PS/2 Mouse */
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# define PIC2_OCW1_IRQ13 (1 << 5) /* IRQ13 Maths Co-Processor */
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# define PIC2_OCW1_IRQ14 (1 << 6) /* IRQ14 Hard Disk Drive */
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# define PIC2_OCW1_IRQ15 (1 << 7) /* IRQ15 Reserved */
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# define PIC2_OCW1_ALL
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/* Operation Control Word 2 selects how the End of Interrupt (EOI) procedure
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* works. The only thing of interest to us in this register is the non-
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* specific EOI command, which we must send at the end of our ISR's.
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*/
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#define PIC1_OCW2 0x20
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#define PIC2_OCW2 0xa0
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# define PIC_OCW2_ACT_SHIFT (0)
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# define PIC_OCW2_ACT_SHIFT (7 << PIC_OCW2_ACT_SHIFT)
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# define PIC1_OCW2_ACT_IRQ0 (0 << PIC_OCW2_ACT_SHIFT) /* Act on IRQ 0 */
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# define PIC1_OCW2_ACT_IRQ1 (1 << PIC_OCW2_ACT_SHIFT) /* Act on IRQ 1 */
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# define PIC1_OCW2_ACT_IRQ2 (2 << PIC_OCW2_ACT_SHIFT) /* Act on IRQ 2 */
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# define PIC1_OCW2_ACT_IRQ3 (3 << PIC_OCW2_ACT_SHIFT) /* Act on IRQ 3 */
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# define PIC1_OCW2_ACT_IRQ4 (4 << PIC_OCW2_ACT_SHIFT) /* Act on IRQ 4 */
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# define PIC1_OCW2_ACT_IRQ5 (5 << PIC_OCW2_ACT_SHIFT) /* Act on IRQ 5 */
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# define PIC1_OCW2_ACT_IRQ6 (6 << PIC_OCW2_ACT_SHIFT) /* Act on IRQ 6 */
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# define PIC1_OCW2_ACT_IRQ7 (7 << PIC_OCW2_ACT_SHIFT) /* Act on IRQ 7 */
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# define PIC2_OCW2_ACT_IRQ8 (0 << PIC_OCW2_ACT_SHIFT) /* Act on IRQ 8 */
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# define PIC2_OCW2_ACT_IRQ9 (1 << PIC_OCW2_ACT_SHIFT) /* Act on IRQ 9 */
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# define PIC2_OCW2_ACT_IRQ10 (2 << PIC_OCW2_ACT_SHIFT) /* Act on IRQ 10 */
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# define PIC2_OCW2_ACT_IRQ11 (3 << PIC_OCW2_ACT_SHIFT) /* Act on IRQ 11 */
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# define PIC2_OCW2_ACT_IRQ12 (4 << PIC_OCW2_ACT_SHIFT) /* Act on IRQ 12 */
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# define PIC2_OCW2_ACT_IRQ13 (5 << PIC_OCW2_ACT_SHIFT) /* Act on IRQ 13 */
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# define PIC2_OCW2_ACT_IRQ14 (6 << PIC_OCW2_ACT_SHIFT) /* Act on IRQ 14 */
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# define PIC2_OCW2_ACT_IRQ15 (7 << PIC_OCW2_ACT_SHIFT) /* Act on IRQ 15 */
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# define PIC_OCW2_EOI_SHIFT (5)
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# define PIC_OCW2_EOI_SHIFT (7 << PIC_OCW2_EOI_SHIFT)
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# define PIC_OCW2_EOI_AUTO (0 << PIC_OCW2_EOI_SHIFT) /* Rotate in Auto EOI Mode (Clear) */
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# define PIC_OCW2_EOI_NONSPEC (1 << PIC_OCW2_EOI_SHIFT) /* Non Specific EOI */
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# define PIC_OCW2_EOI_SPEC (3 << PIC_OCW2_EOI_SHIFT) /* Specific EOI */
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# define PIC_OCW2_EOI_RAUTO (4 << PIC_OCW2_EOI_SHIFT) /* Rotate in Auto EOI Mode (Set) */
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# define PIC_OCW2_EOI_RNSPEC (5 << PIC_OCW2_EOI_SHIFT) /* Rotate on Non-Specific EOI */
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# define PIC_OCW2_EOI_PRIO (6 << PIC_OCW2_EOI_SHIFT) /* Set Priority Command (Use Bits 2:0) */
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# define PIC_OCW2_EOI_RSPEC (7 << PIC_OCW2_EOI_SHIFT) /* Rotate on Specific EOI (Use Bits 2:0) */
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/* Operation Control Word 3. Bits 0 and 1 bitsenable us to read the status
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* of the Interrupt Request Register (IRR) and the In-Service Register (ISR).
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* This is done by setting the appropriate bits correctly and reading the
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* register at the Base Address.
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*
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* For example if we wanted to read the In-Service Register (ISR), then we
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* would set both bits 1 and 0 to 1. The next read to the base register,
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* (0x20 for PIC1 or 0xa0 for PIC2) will return the status of the In-Service
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* Register.
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*/
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#define PIC1_OCW3 0x20
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#define PIC2_OCW3 0xa0
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# define PIC_OCW3_PCMD_SHIFT (0) /* Poll command */
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# define PIC_OCW3_PCMD_MASK (3 << PIC_OCW3_PCMD_SHIFT)
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# define PIC_OCW3_PCMD_IRR (2 << PIC_OCW3_PCMD_SHIFT) /* Next Read Returns Interrupt Request Register */
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# define PIC_OCW3_PCMD_ISR (3 << PIC_OCW3_PCMD_SHIFT) /* Next Read Returns In-Service Register */
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# define PIC_OCW3_POLLCMD (1 << 2) /* Poll command */
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# define PIC_OCW3_ONE (1 << 3) /* Must be set to 1 */
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# define PIC_OCW3_SM_SHIFT (5)
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# define PIC_OCW3_SM_SHIFT (3 << PIC_OCW3_SM_SHIFT)
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# define PIC_OCW3_RSM (2 << PIC_OCW3_SM_SHIFT) /* Reset Special Mask */
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# define PIC_OCW3_SSM (3 << PIC_OCW3_SM_SHIFT) /* Set Special Mask */
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/* If the PIC has been reset, it must be initialized with 2 to 4 Initialization
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* Command Words (ICW) before it will accept and process Interrupt Requests. The
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* following outlines the four possible Initialization Command Words.
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*/
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#define PIC1_ICW1 0x20
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#define PIC2_ICW1 0xa0
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# define PIC_ICW1_ICW4 (1 << 0) /* Will be Sending ICW4 (no ICW4) */
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# define PIC_ICW1_SINGLE (1 << 1) /* Single PIC (vs. Cascaded pics) */
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# define PIC_ICW1_INTERVAL (1 << 2) /* Call Address Interval of 4 (vs 8) */
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# define PIC_ICW1_LEVEL (1 << 3) /* Level Triggered Interrupts (vs Edge) */
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# define PIC_ICW1_ICW1 (1 << 4) /* Must be set to 1 for ICW1 */
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# define PIC_ICW1_VEC_SHIFT (5) /* Interrupt Vector Addresses for MCS-80/85 Mode */
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# define PIC_ICW1_VEC_MASK (7 << PIC_ICW1_VEC_SHIFT)
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/* Initialization Command Word 2 (ICW2) selects which vector information is
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* released onto the bus, during the 2nd INTA Pulse. Using the 8086 mode,
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* only bits 7:3 need to be used. This will be 00001000 (0x08) for PIC1 and
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* 01110000 (0x70) for PIC2. If you wish to relocate the IRQ Vector Table,
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* then you can use this register.
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*/
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#define PIC1_ICW2 0x21
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#define PIC2_ICW2 0xa1
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/* There are two different Initialization Command Word 3's. One is used, if
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* the PIC is a master, while the other is used for slaves.
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*/
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#define PIC1_ICW3 0x21
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#define PIC2_ICW3 0xa1
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/* Master ICW3 */
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# define PIC1_ICW3_IRQ0 (1 << 0) /* IRQ0 is connected to a Slave */
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# define PIC1_ICW3_IRQ1 (1 << 1) /* IRQ1 is connected to a Slave */
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# define PIC1_ICW3_IRQ2 (1 << 2) /* IRQ2 is connected to a Slave */
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# define PIC1_ICW3_IRQ3 (1 << 3) /* IRQ3 is connected to a Slave */
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# define PIC1_ICW3_IRQ4 (1 << 4) /* IRQ4 is connected to a Slave */
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# define PIC1_ICW3_IRQ5 (1 << 5) /* IRQ5 is connected to a Slave */
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# define PIC1_ICW3_IRQ6 (1 << 6) /* IRQ6 is connected to a Slave */
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# define PIC1_ICW3_IRQ7 (1 << 7) /* IRQ7 is connected to a Slave */
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/* And for the slave device, the ICW3 below is used. */
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# define PIC_ICW3_SID_MASK (0) /* Slave ID */
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# define PIC_ICW3_SID_SHIFT (7 << PIC_ICW3_SID_MASK)
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# define PIC_ICW3_SID0 (0 << PIC_ICW3_SID_MASK) /* Slave 0 */
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# define PIC_ICW3_SID1 (1 << PIC_ICW3_SID_MASK) /* Slave 1 */
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# define PIC_ICW3_SID2 (2 << PIC_ICW3_SID_MASK) /* Slave 2 */
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# define PIC_ICW3_SID3 (3 << PIC_ICW3_SID_MASK) /* Slave 3 */
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# define PIC_ICW3_SID4 (4 << PIC_ICW3_SID_MASK) /* Slave 4 */
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# define PIC_ICW3_SID5 (5 << PIC_ICW3_SID_MASK) /* Slave 5 */
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# define PIC_ICW3_SID6 (6 << PIC_ICW3_SID_MASK) /* Slave 6 */
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# define PIC_ICW3_SID7 (7 << PIC_ICW3_SID_MASK) /* Slave 7 */
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#define PIC1_ICW4 0x21
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#define PIC2_ICW4 0xa1
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# define PIC_ICW4_FNM (1 << 4) /* Special Fully Nested Mode */
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# define PIC_ICW4_BMODE_SHIFT (2) /* Bufferd mode */
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# define PIC_ICW4_BMODE_MASK (3 << PIC_ICW4_BMODE_SHIFT)
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# define PIC_ICW4_BMODE_NON (0 << PIC_ICW4_BMODE_SHIFT) /* Non - Buffered Mode */
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# define PIC_ICW4_BMODE_SLAVE (2 << PIC_ICW4_BMODE_SHIFT) /* Buffered Mode - Slave */
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# define PIC_ICW4_BMODE_MSTR (3 << PIC_ICW4_BMODE_SHIFT) /* Buffered Mode - Master */
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# define PIC_ICW4_AEOI (1 << 1) /* Auto EOI */
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# define PIC_ICW4_808xMODE (1 << 0) /* 8086/8080 Mode (vs MCS-80/85) */
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/* Interrupt Mask Register */
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#define PIC1_IMR 0x21
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#define PIC2_IMR 0xa1
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# define PIC1_IMR_IRQ0 (1 << 0) /* IRQ0 System Timer */
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# define PIC1_IMR_IRQ1 (1 << 1) /* IRQ1 Keyboard */
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# define PIC1_IMR_IRQ2 (1 << 2) /* IRQ2 PIC2 */
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# define PIC1_IMR_IRQ3 (1 << 3) /* IRQ3 Serial Port */
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# define PIC1_IMR_IRQ4 (1 << 4) /* IRQ4 Serial Port */
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# define PIC1_IMR_IRQ5 (1 << 5) /* IRQ5 Reserved/Sound Card */
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# define PIC1_IMR_IRQ6 (1 << 6) /* IRQ6 Floppy Disk Controller */
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# define PIC1_IMR_IRQ7 (1 << 7) /* IRQ7 Parallel Port */
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# define PIC1_IMR_ALL 0xff
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# define PIC2_IMR_IRQ8 (1 << 0) /* IRQ8 Real Time Clock */
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# define PIC2_IMR_IRQ9 (1 << 1) /* IRQ9 Redirected IRQ2 */
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# define PIC2_IMR_IRQ10 (1 << 2) /* IRQ10 Reserved */
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# define PIC2_IMR_IRQ11 (1 << 3) /* IRQ11 Reserved */
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# define PIC2_IMR_IRQ12 (1 << 4) /* IRQ12 PS/2 Mouse */
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# define PIC2_IMR_IRQ13 (1 << 5) /* IRQ13 Maths Co-Processor */
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# define PIC2_IMR_IRQ14 (1 << 6) /* IRQ14 Hard Disk Drive */
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# define PIC2_IMR_IRQ15 (1 << 7) /* IRQ15 Reserved */
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# define PIC2_IMR_ALL 0xff
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/* Programmable Interrupt Timer Definitions */
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#define PIT_REG_COUNTER0 0x40
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#define PIT_REG_COUNTER1 0x41
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#define PIT_REG_COUNTER2 0x42
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#define PIT_REG_COMMAND 0x43
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/* PIT command bit defintions */
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# define PIT_OCW_BINCOUNT_BCD (1 << 0) /* vs binary */
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# define PIT_OCW_MODE_SHIFT (1)
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# define PIT_OCW_MODE_MASK (7 << PIT_OCW_MODE_SHIFT)
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# define PIT_OCW_MODE_TMCNT (0 << PIT_OCW_MODE_SHIFT) /* Terminal count */
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# define PIT_OCW_MODE_ONESHOT (1 << PIT_OCW_MODE_SHIFT) /* One shot */
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# define PIT_OCW_MODE_RATEGEN (2 << PIT_OCW_MODE_SHIFT) /* Rate gen */
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# define PIT_OCW_MODE_SQUARE (3 << PIT_OCW_MODE_SHIFT) /* Square wave generation */
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# define PIT_OCW_MODE_SWTRIG (4 << PIT_OCW_MODE_SHIFT) /* Software trigger */
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# define PIT_OCW_MODE_HWTRIG (5 << PIT_OCW_MODE_SHIFT) /* Hardware trigger */
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# define PIT_OCW_RL_SHIFT (4)
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# define PIT_OCW_RL_MASK (3 << PIT_OCW_RL_SHIFT)
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# define PIT_OCW_RL_LATCH (0 << PIT_OCW_RL_SHIFT)
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# define PIT_OCW_RL_LSBONLY (1 << PIT_OCW_RL_SHIFT)
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# define PIT_OCW_RL_MSBONLY (2 << PIT_OCW_RL_SHIFT)
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# define PIT_OCW_RL_DATA (3 << PIT_OCW_RL_SHIFT)
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# define PIT_OCW_COUNTER_SHIFT (6)
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# define PIT_OCW_COUNTER_MASK (3 << PIT_OCW_COUNTER_SHIFT)
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# define PIT_OCW_COUNTER_0 (0 << PIT_OCW_COUNTER_SHIFT)
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# define PIT_OCW_COUNTER_1 (1 << PIT_OCW_COUNTER_SHIFT)
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# define PIT_OCW_COUNTER_2 (2 << PIT_OCW_COUNTER_SHIFT)
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/****************************************************************************
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* Public Types
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****************************************************************************/
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/* GDT data structures ******************************************************
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*
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* The Global Descriptor Table or GDT is a data structure used by Intel x86-
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* family processors starting with the 80286 in order to define the
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* characteristics of the various memory areas used during program execution,
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* for example the base address, the size and access privileges like
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* executability and writability. These memory areas are called segments in
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* Intel terminology.
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*/
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/* This structure defines one segment */
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struct gdt_entry_s
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{
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uint16_t lowlimit; /* The lower 16 bits of the limit */
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uint16_t lowbase; /* The lower 16 bits of the base */
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uint8_t midbase; /* The next 8 bits of the base */
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uint8_t access; /* Access flags, determine ring segment can be used in */
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uint8_t granularity;
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uint8_t hibase; /* The last 8 bits of the base */
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} __attribute__((packed));
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/* This structure refers to the array of GDT entries, and is in the format
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* required by the lgdt instruction.
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*/
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struct gdt_ptr_s
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{
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uint16_t limit; /* The upper 16 bits of all selector limits */
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uint32_t base; /* The address of the first GDT entry */
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} __attribute__((packed));
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/* IDT data structures ******************************************************
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*
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* The Interrupt Descriptor Table (IDT) is a data structure used by the x86
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* architecture to implement an interrupt vector table. The IDT is used by the
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* processor to determine the correct response to interrupts and exceptions.
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*/
|
|
|
|
struct idt_entry_s
|
|
{
|
|
uint16_t lobase; /* Lower 16-bits of vector address for interrupt */
|
|
uint16_t sel; /* Kernel segment selector */
|
|
uint8_t zero; /* This must always be zero */
|
|
uint8_t flags; /* (See documentation) */
|
|
uint16_t hibase; /* Upper 16-bits of vector address for interrupt */
|
|
} __attribute__((packed));
|
|
|
|
/* A struct describing a pointer to an array of interrupt handlers. This is
|
|
* in a format suitable for giving to 'lidt'.
|
|
*/
|
|
|
|
struct idt_ptr_s
|
|
{
|
|
uint16_t limit;
|
|
uint32_t base; /* The address of the first GDT entry */
|
|
} __attribute__((packed));
|
|
|
|
/****************************************************************************
|
|
* Inline functions
|
|
****************************************************************************/
|
|
|
|
#ifndef __ASSEMBLY__
|
|
|
|
/* Return stack pointer */
|
|
|
|
static inline uint32_t up_getsp()
|
|
{
|
|
uint32_t regval;
|
|
|
|
asm volatile(
|
|
"\tmovl %%esp, %0\n"
|
|
: "=rm" (regval)
|
|
:
|
|
: "memory");
|
|
return regval;
|
|
}
|
|
|
|
/* Get segment registers */
|
|
|
|
static inline uint32_t up_getds()
|
|
{
|
|
uint32_t regval;
|
|
|
|
asm volatile(
|
|
"\tmov %%ds, %0\n"
|
|
: "=rm" (regval)
|
|
:
|
|
: "memory");
|
|
return regval;
|
|
}
|
|
|
|
static inline uint32_t up_getcs()
|
|
{
|
|
uint32_t regval;
|
|
|
|
asm volatile(
|
|
"\tmov %%cs, %0\n"
|
|
: "=rm" (regval)
|
|
:
|
|
: "memory");
|
|
return regval;
|
|
}
|
|
|
|
static inline uint32_t up_getss()
|
|
{
|
|
uint32_t regval;
|
|
|
|
asm volatile(
|
|
"\tmov %%ss, %0\n"
|
|
: "=rm" (regval)
|
|
:
|
|
: "memory");
|
|
return regval;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Public Types
|
|
****************************************************************************/
|
|
|
|
/****************************************************************************
|
|
* Public Variables
|
|
****************************************************************************/
|
|
|
|
/****************************************************************************
|
|
* Public Function Prototypes
|
|
****************************************************************************/
|
|
|
|
#ifdef __cplusplus
|
|
#define EXTERN extern "C"
|
|
extern "C" {
|
|
#else
|
|
#define EXTERN extern
|
|
#endif
|
|
|
|
EXTERN void gdt_flush(uint32_t gdt_addr);
|
|
EXTERN void idt_flush(uint32_t idt_addr);
|
|
|
|
#undef EXTERN
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* __ASSEMBLY__ */
|
|
#endif /* __ARCH_X86_INCLUDE_I486_ARCH_H */
|
|
|