Abdelatif Guettouche 73a1e0fc58 arch/xtensa: Refactor exceptions' entry and exit. ... Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>		2022-06-15 18:07:51 +03:00
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common	arch/xtensa: Refactor exceptions' entry and exit.	2022-06-15 18:07:51 +03:00
esp32	arch/xtensa/esp32_rtc_lowerhalf.c: nitialize ret variable to avoid	2022-06-15 21:29:55 +08:00
esp32s2	arch/xtensa: Don't build xtensa_coproc.S, it has only macros and is	2022-06-13 21:32:23 +03:00
esp32s3	arch/xtensa: Don't build xtensa_coproc.S, it has only macros and is	2022-06-13 21:32:23 +03:00
lx6	Move "-nostartfiles -nodefaultlibs" from Make.defs to Toolchian.defs	2022-05-18 08:26:02 -04:00
lx7	Move "-nostartfiles -nodefaultlibs" from Make.defs to Toolchian.defs	2022-05-18 08:26:02 -04:00
.gitignore
Makefile	Fix CONFIG_ALLSYMS for arm, risc-v and xtensa after #5496	2022-06-13 11:39:06 +08:00