730f7450b7
Squashed commit of the following:
Remove final references to CC3200 from the repository.
arch/arm/include/tiva: Remove all CC3200 support.
arch/arm/src/tiva: Remove all CC3200 support.
configs/cc3200-launchpad: Remove the board support directory.
367 lines
20 KiB
C
367 lines
20 KiB
C
/************************************************************************************
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* arch/arm/include/tiva/chip.h
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*
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* Copyright (C) 2009-2010, 2013-2014 Gregory Nutt. All rights reserved.
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* Authors: Gregory Nutt <gnutt@nuttx.org>
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* Jose Pablo Carballo <jcarballo@nx-engineering.com>
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* Jim Ewing <jim@droidifi.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_TIVA_CHIP_H
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#define __ARCH_ARM_INCLUDE_TIVA_CHIP_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Get customizations for each supported chip (only the LM3S6918 and 65 right now) */
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#if defined(CONFIG_ARCH_CHIP_LM3S6918)
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# define LM3S 1 /* LM3S family */
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# undef LM4F /* Not LM4F family */
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# undef TM4C /* Not TM4C family */
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# define TIVA_NTIMERS 4 /* Four 16/32-bit timers */
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# define TIVA_NWIDETIMERS 0 /* No 32/64-bit timers */
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# define TIVA_NWDT 1 /* One watchdog timer */
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# define TIVA_NETHCONTROLLERS 1 /* One Ethernet controller */
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# define TIVA_NLCD 0 /* No LCD controller */
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# undef TIVA_ETHTS /* No timestamp register */
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# define TIVA_NSSI 2 /* Two SSI modules */
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# define TIVA_NUARTS 2 /* Two UART modules */
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# define TIVA_NI2C 2 /* Two I2C modules */
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# define TIVA_NADC 1 /* One ADC module */
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# define TIVA_NPWM 0 /* No PWM generator modules */
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# define TIVA_NQEI 0 /* No quadrature encoders */
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# define TIVA_NPORTS 8 /* 8 Ports (GPIOA-H) 5-38 GPIOs */
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# define TIVA_NCANCONTROLLER 0 /* No CAN controllers */
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# define TIVA_NUSBOTGFS 0 /* No USB 2.0 OTG FS */
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# define TIVA_NUSBOTGHS 0 /* No USB 2.0 OTG HS */
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# define TIVA_NCRC 0 /* No CRC module */
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# define TIVA_NAES 0 /* No AES module */
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# define TIVA_NDES 0 /* No DES module */
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# define TIVA_NHASH 0 /* No SHA1/MD5 hash module */
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#elif defined(CONFIG_ARCH_CHIP_LM3S6432)
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# define LM3S 1 /* LM3S family */
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# undef LM4F /* Not LM4F family */
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# undef TM4C /* Not TM4C family */
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# define TIVA_NTIMERS 3 /* Three 16/32-bit timers */
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# define TIVA_NWIDETIMERS 0 /* No 32/64-bit timers */
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# define TIVA_NWDT 1 /* One watchdog timer */
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# define TIVA_NETHCONTROLLERS 1 /* One Ethernet controller */
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# define TIVA_NLCD 0 /* No LCD controller */
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# undef TIVA_ETHTS /* No timestamp register */
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# define TIVA_NSSI 1 /* One SSI module */
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# define TIVA_NUARTS 2 /* Two UART modules */
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# define TIVA_NI2C 1 /* Two I2C modules */
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# define TIVA_NADC 1 /* One ADC module */
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# define TIVA_NPWM 1 /* One PWM generator module */
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# define TIVA_NQEI 0 /* No quadrature encoders */
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# define TIVA_NPORTS 7 /* 7 Ports (GPIOA-G), 0-42 GPIOs */
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# define TIVA_NCANCONTROLLER 0 /* No CAN controllers */
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# define TIVA_NUSBOTGFS 0 /* No USB 2.0 OTG FS */
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# define TIVA_NUSBOTGHS 0 /* No USB 2.0 OTG HS */
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# define TIVA_NCRC 0 /* No CRC module */
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# define TIVA_NAES 0 /* No AES module */
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# define TIVA_NDES 0 /* No DES module */
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# define TIVA_NHASH 0 /* No SHA1/MD5 hash module */
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#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
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# define LM3S 1 /* LM3S family */
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# undef LM4F /* Not LM4F family */
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# undef TM4C /* Not TM4C family */
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# define TIVA_NTIMERS 4 /* Four 16/32-bit timers */
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# define TIVA_NWIDETIMERS 0 /* No 32/64-bit timers */
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# define TIVA_NWDT 1 /* One watchdog timer */
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# define TIVA_NETHCONTROLLERS 1 /* One Ethernet controller */
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# define TIVA_NLCD 0 /* No LCD controller */
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# undef TIVA_ETHTS /* No timestamp register */
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# define TIVA_NSSI 1 /* One SSI module */
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# define TIVA_NUARTS 3 /* Three UART modules */
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# define TIVA_NI2C 2 /* Two I2C modules */
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# define TIVA_NADC 1 /* One ADC module */
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# define TIVA_NPWM 3 /* Three PWM generator modules */
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# define TIVA_NQEI 2 /* Two quadrature encoders */
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# define TIVA_NPORTS 7 /* 7 Ports (GPIOA-G), 0-42 GPIOs */
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# define TIVA_NCANCONTROLLER 0 /* No CAN controllers */
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# define TIVA_NUSBOTGFS 0 /* No USB 2.0 OTG FS */
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# define TIVA_NUSBOTGHS 0 /* No USB 2.0 OTG HS */
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# define TIVA_NCRC 0 /* No CRC module */
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# define TIVA_NAES 0 /* No AES module */
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# define TIVA_NDES 0 /* No DES module */
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# define TIVA_NHASH 0 /* No SHA1/MD5 hash module */
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#elif defined(CONFIG_ARCH_CHIP_LM3S9B96)
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# define LM3S 1 /* LM3S family */
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# undef LM4F /* Not LM4F family */
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# undef TM4C /* Not TM4C family */
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# define TIVA_NTIMERS 4 /* Four 16/32-bit timers */
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# define TIVA_NWIDETIMERS 0 /* No 32/64-bit timers */
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# define TIVA_NWDT 1 /* One watchdog timer */
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# define TIVA_NETHCONTROLLERS 1 /* One Ethernet controller */
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# define TIVA_NLCD 0 /* No LCD controller */
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# undef TIVA_ETHTS /* No timestamp register */
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# define TIVA_NSSI 2 /* Two SSI modules */
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# define TIVA_NUARTS 3 /* Three UART modules */
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# define TIVA_NI2C 2 /* Two I2C modules */
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# define TIVA_NADC 2 /* Two ADC module */
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# define TIVA_CAN 2 /* Two CAN module */
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# define TIVA_NPWM 4 /* Four PWM generator modules */
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# define TIVA_NQEI 2 /* Two quadrature encoders */
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# define TIVA_NPORTS 9 /* 9 Ports (GPIOA-H,J) 0-65 GPIOs */
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# define TIVA_NCANCONTROLLER 0 /* No CAN controllers */
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# define TIVA_NUSBOTGFS 0 /* No USB 2.0 OTG FS */
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# define TIVA_NUSBOTGHS 0 /* No USB 2.0 OTG HS */
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# define TIVA_NCRC 0 /* No CRC module */
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# define TIVA_NAES 0 /* No AES module */
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# define TIVA_NDES 0 /* No DES module */
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# define TIVA_NHASH 0 /* No SHA1/MD5 hash module */
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#elif defined(CONFIG_ARCH_CHIP_LM3S8962)
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# define LM3S 1 /* LM3S family */
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# undef LM4F /* Not LM4F family */
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# undef TM4C /* Not TM4C family */
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# define TIVA_NTIMERS 6 /* Four 16/32-bit timers */
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# define TIVA_NWIDETIMERS 0 /* No 32/64-bit timers */
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# define TIVA_NWDT 1 /* One watchdog timer */
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# define TIVA_NETHCONTROLLERS 1 /* One Ethernet controller */
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# define TIVA_NLCD 0 /* No LCD controller */
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# define TIVA_NSSI 1 /* One SSI module */
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# define TIVA_NUARTS 3 /* Two UART modules */
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# define TIVA_NI2C 2 /* One I2C module */
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# define TIVA_NADC 1 /* One ADC module */
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# define TIVA_NPWM 3 /* Three PWM generator modules */
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# define TIVA_NQEI 2 /* Two quadrature encoders */
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# define TIVA_NPORTS 7 /* 7 Ports (GPIOA-G), 5-42 GPIOs */
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# define TIVA_NCANCONTROLLER 1 /* One CAN controller */
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# define TIVA_NUSBOTGFS 0 /* No USB 2.0 OTG FS */
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# define TIVA_NUSBOTGHS 0 /* No USB 2.0 OTG HS */
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# define TIVA_NCRC 0 /* No CRC module */
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# define TIVA_NAES 0 /* No AES module */
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# define TIVA_NDES 0 /* No DES module */
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# define TIVA_NHASH 0 /* No SHA1/MD5 hash module */
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#elif defined(CONFIG_ARCH_CHIP_LM4F120)
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# undef LM3S /* Not LM3S family */
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# define LM4F 1 /* LM4F family */
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# undef TM4C /* Not TM4C family */
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# define TIVA_NTIMERS 6 /* Six 16/32-bit timers */
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# define TIVA_NWIDETIMERS 6 /* Six 32/64-bit timers */
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# define TIVA_NWDT 2 /* Two watchdog timer timers */
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# define TIVA_NETHCONTROLLERS 0 /* No Ethernet controller */
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# define TIVA_NLCD 0 /* No LCD controller */
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# define TIVA_NSSI 4 /* Four SSI module */
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# define TIVA_NUARTS 8 /* Eight UART modules */
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# define TIVA_NI2C 4 /* Four I2C modules */
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# define TIVA_NADC 2 /* Two ADC modules */
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# define TIVA_NPWM 0 /* No PWM generator modules */
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# define TIVA_NQEI 0 /* No quadrature encoders */
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# define TIVA_NPORTS 6 /* 6 Ports (GPIOA-F), 0-43 GPIOs */
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# define TIVA_NCANCONTROLLER 1 /* One CAN controller */
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# define TIVA_NUSBOTGFS 0 /* No USB 2.0 OTG FS */
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# define TIVA_NUSBOTGHS 0 /* No USB 2.0 OTG HS */
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# define TIVA_NCRC 0 /* No CRC module */
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# define TIVA_NAES 0 /* No AES module */
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# define TIVA_NDES 0 /* No DES module */
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# define TIVA_NHASH 0 /* No SHA1/MD5 hash module */
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#elif defined(CONFIG_ARCH_CHIP_TM4C123GH6PGE) || defined(CONFIG_ARCH_CHIP_TM4C123GH6PZ) || \
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defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB)
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# undef LM3S /* Not LM3S family */
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# undef LM4F /* Not LM4F family */
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# define TM4C 1 /* TM4C family */
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# define TIVA_NTIMERS 6 /* Six 16/32-bit timers */
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# define TIVA_NWIDETIMERS 6 /* Six 32/64-bit timers */
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# define TIVA_NWDT 2 /* Two watchdog timers */
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# define TIVA_NETHCONTROLLERS 0 /* No Ethernet controller */
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# define TIVA_NLCD 0 /* No LCD controller */
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# define TIVA_NSSI 4 /* Four SSI module */
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# define TIVA_NUARTS 8 /* Eight UART modules */
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# define TIVA_NI2C 6 /* Six I2C modules */
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# define TIVA_NADC 2 /* Two ADC modules */
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# define TIVA_NPWM 2 /* Two PWM generator modules */
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# define TIVA_NQEI 1 /* One quadrature encoders */
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# define TIVA_NPORTS 15 /* Fifteen Ports (GPIOA-H, J-N, P-Q) */
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# define TIVA_NCANCONTROLLER 2 /* Two CAN controllers */
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# define TIVA_NUSBOTGFS 1 /* One USB 2.0 OTG FS */
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# define TIVA_NUSBOTGHS 0 /* No USB 2.0 OTG HS */
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# define TIVA_NCRC 0 /* No CRC module */
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# define TIVA_NAES 0 /* No AES module */
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# define TIVA_NDES 0 /* No DES module */
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# define TIVA_NHASH 0 /* No SHA1/MD5 hash module */
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#elif defined(CONFIG_ARCH_CHIP_TM4C123GH6PMI)
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# undef LM3S /* Not LM3S family */
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# undef LM4F /* Not LM4F family */
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# define TM4C 1 /* TM4C family */
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# define TIVA_NTIMERS 6 /* Six 16/32-bit timers */
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# define TIVA_NWIDETIMERS 6 /* Six 32/64-bit timers */
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# define TIVA_NWDT 2 /* Two watchdog timers */
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# define TIVA_NETHCONTROLLERS 0 /* No Ethernet controller */
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# define TIVA_NLCD 0 /* No LCD controller */
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# define TIVA_NSSI 4 /* Four SSI module */
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# define TIVA_NUARTS 8 /* Eight UART modules */
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# define TIVA_NI2C 4 /* Four I2C modules */
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# define TIVA_NADC 2 /* Two ADC modules */
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# define TIVA_NPWM 2 /* Two PWM generator modules */
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# define TIVA_NQEI 2 /* Two quadrature encoders */
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# define TIVA_NPORTS 6 /* Six Ports (GPIOA-F) */
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# define TIVA_NCANCONTROLLER 2 /* Two CAN controllers */
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# define TIVA_NUSBOTGFS 1 /* One USB 2.0 OTG FS */
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# define TIVA_NUSBOTGHS 0 /* No USB 2.0 OTG HS */
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# define TIVA_NCRC 0 /* No CRC module */
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# define TIVA_NAES 0 /* No AES module */
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# define TIVA_NDES 0 /* No DES module */
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# define TIVA_NHASH 0 /* No SHA1/MD5 hash module */
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#elif defined(CONFIG_ARCH_CHIP_TM4C1294NC)
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# undef LM3S /* Not LM3S family */
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# undef LM4F /* Not LM4F family */
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# define TM4C 1 /* TM4C family */
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# define TIVA_NTIMERS 8 /* Eight Dual 16/32-bit timers A/B */
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# define TIVA_NWIDETIMERS 0 /* No 32/64-bit timers */
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# define TIVA_NWDT 2 /* Two watchdog timers */
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# define TIVA_NETHCONTROLLERS 1 /* One 10/100Mbit Ethernet controller */
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# define TIVA_NLCD 1 /* One LCD controller */
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# define TIVA_NSSI 4 /* Four SSI modules */
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# define TIVA_NUARTS 8 /* Eight UART modules */
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# define TIVA_NI2C 10 /* Ten I2C modules */
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# define TIVA_NADC 2 /* Two ADC modules */
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# define TIVA_NPWM 4 /* Four PWM generator modules */
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# define TIVA_NQEI 1 /* One quadrature encoders */
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# define TIVA_NPORTS 15 /* Fifteen Ports (GPIOA-H, J-N, P-Q) */
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# define TIVA_NCANCONTROLLER 2 /* Two CAN controllers */
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# define TIVA_NUSBOTGFS 0 /* No USB 2.0 OTG FS */
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# define TIVA_NUSBOTGHS 1 /* One USB 2.0 OTG HS */
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# define TIVA_NCRC 1 /* One CRC module */
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# define TIVA_NAES 0 /* No AES module */
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# define TIVA_NDES 0 /* No DES module */
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# define TIVA_NHASH 0 /* No SHA1/MD5 hash module */
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#elif defined(CONFIG_ARCH_CHIP_TM4C129XNC)
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# undef LM3S /* Not LM3S family */
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# undef LM4F /* Not LM4F family */
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# define TM4C 1 /* TM4C family */
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# define TIVA_NTIMERS 8 /* Eight Dual 16/32-bit timers A/B */
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# define TIVA_NWIDETIMERS 0 /* No 32/64-bit timers */
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# define TIVA_NWDT 2 /* Two watchdog timers */
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# define TIVA_NETHCONTROLLERS 1 /* One 10/100Mbit Ethernet controller */
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# define TIVA_NLCD 1 /* One LCD controller */
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# define TIVA_NSSI 4 /* Four SSI modules */
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# define TIVA_NUARTS 8 /* Eight UART modules */
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# define TIVA_NI2C 10 /* Ten I2C modules */
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# define TIVA_NADC 2 /* Two ADC modules */
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# define TIVA_NPWM 4 /* Four PWM generator modules */
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# define TIVA_NQEI 1 /* One quadrature encoder module */
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# define TIVA_NPORTS 18 /* Eighteen Ports (GPIOA-H, J-N, P-T) */
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# define TIVA_NCANCONTROLLER 2 /* Two CAN controllers */
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# define TIVA_NUSBOTGFS 0 /* No USB 2.0 OTG FS */
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# define TIVA_NUSBOTGHS 1 /* One USB 2.0 OTG HS */
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# define TIVA_NCRC 1 /* One CRC module */
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# define TIVA_NAES 1 /* One AES module */
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# define TIVA_NDES 1 /* One DES module */
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# define TIVA_NHASH 1 /* One SHA1/MD5 hash module */
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#else
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# error "Capabilities not specified for this TIVA/Stellaris chip"
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#endif
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/* The TIVA/Stellaris only supports 8 priority levels. The hardware priority
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* mechanism will only look at the upper N bits of the 8-bit priority level
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* (where N is 3 for the Tiva/Stellaris family), so any prioritization must be
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* performed in those bits. The default priority level is set to the middle
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* value
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*/
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#define NVIC_SYSH_PRIORITY_MIN 0xe0 /* Bits [7:5] set in minimum priority */
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#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
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#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
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#define NVIC_SYSH_PRIORITY_STEP 0x20 /* Three bits of interrupt priority used */
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/* If CONFIG_ARMV7M_USEBASEPRI is selected, then interrupts will be disabled
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* by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so that most
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* interrupts will not have execution priority. SVCall must have execution
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* priority in all cases.
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*
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* In the normal cases, interrupts are not nest-able and all interrupts run
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* at an execution priority between NVIC_SYSH_PRIORITY_MIN and
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* NVIC_SYSH_PRIORITY_MAX (with NVIC_SYSH_PRIORITY_MAX reserved for SVCall).
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*
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* If, in addition, CONFIG_ARCH_HIPRI_INTERRUPT is defined, then special
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* high priority interrupts are supported. These are not "nested" in the
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* normal sense of the word. These high priority interrupts can interrupt
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* normal processing but execute outside of OS (although they can "get back
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* into the game" via a PendSV interrupt).
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*
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* In the normal course of things, interrupts must occasionally be disabled
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* using the up_irq_save() inline function to prevent contention in use of
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* resources that may be shared between interrupt level and non-interrupt
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* level logic. Now the question arises, if CONFIG_ARCH_HIPRI_INTERRUPT,
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* do we disable all interrupts (except SVCall), or do we only disable the
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* "normal" interrupts. Since the high priority interrupts cannot interact
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* with the OS, you may want to permit the high priority interrupts even if
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* interrupts are disabled. The setting CONFIG_ARCH_INT_DISABLEALL can be
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* used to select either behavior:
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*
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* ----------------------------+--------------+----------------------------
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* CONFIG_ARCH_HIPRI_INTERRUPT | NO | YES
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* ----------------------------+--------------+--------------+-------------
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* CONFIG_ARCH_INT_DISABLEALL | N/A | YES | NO
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* ----------------------------+--------------+--------------+-------------
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* | | | SVCall
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* | SVCall | SVCall | HIGH
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* Disable here and below --------> MAXNORMAL ---> HIGH --------> MAXNORMAL
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* | | MAXNORMAL |
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* ----------------------------+--------------+--------------+-------------
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*/
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#if defined(CONFIG_ARCH_HIPRI_INTERRUPT) && defined(CONFIG_ARCH_INT_DISABLEALL)
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# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + 2*NVIC_SYSH_PRIORITY_STEP)
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# define NVIC_SYSH_HIGH_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP)
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# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_HIGH_PRIORITY
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# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX
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#else
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# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP)
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# define NVIC_SYSH_HIGH_PRIORITY NVIC_SYSH_PRIORITY_MAX
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# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_MAXNORMAL_PRIORITY
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# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX
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#endif
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#endif /* __ARCH_ARM_INCLUDE_TIVA_CHIP_H */
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