252 lines
8.4 KiB
C
252 lines
8.4 KiB
C
/****************************************************************************
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* boards/arm/stm32f7/stm32f746g-disco/src/stm32_extmem.c
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*
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* Copyright (C) 2018 Marcin Wyrwas. All rights reserved.
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* Author: Marcin Wyrwas <mvp1@wp.pl>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <assert.h>
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#include <debug.h>
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#include "chip.h"
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#include "arm_internal.h"
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#include "stm32_fmc.h"
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#include "stm32_gpio.h"
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#include "stm32_rcc.h"
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#include "stm32f746g-disco.h"
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#include <arch/board/board.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#ifndef CONFIG_STM32F7_FMC
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# warning "FMC is not enabled"
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#endif
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#if STM32F7_NGPIO < 7
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# error "Required GPIO ports not enabled"
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#endif
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#define STM32_FMC_NADDRCONFIGS 22
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#define STM32_FMC_NDATACONFIGS 16
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#define STM32_SDRAM_CLKEN FMC_SDCMR_CTB1 | FMC_SDCMR_MODE_CLK_ENABLE
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#define STM32_SDRAM_PALL FMC_SDCMR_CTB1 | FMC_SDCMR_MODE_PALL
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#define STM32_SDRAM_REFRESH FMC_SDCMR_CTB1 | FMC_SDCMR_MODE_AUTO_REFRESH |\
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FMC_SDCMR_NRFS(8)
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#define STM32_SDRAM_MODEREG FMC_SDCMR_CTB1 | FMC_SDCMR_MODE_LOAD_MODE |\
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FMC_SDCMR_MRD_BURST_LENGTH_1 | \
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FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL |\
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FMC_SDCMR_MRD_CAS_LATENCY_3 |\
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FMC_SDCMR_MRD_OPERATING_MODE_STANDARD |\
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FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/* GPIO configurations common to most external memories */
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static const uint32_t g_addressconfig[STM32_FMC_NADDRCONFIGS] =
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{
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GPIO_FMC_A0, GPIO_FMC_A1, GPIO_FMC_A2, GPIO_FMC_A3, GPIO_FMC_A4,
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GPIO_FMC_A5, GPIO_FMC_A6, GPIO_FMC_A7, GPIO_FMC_A8, GPIO_FMC_A9,
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GPIO_FMC_A10, GPIO_FMC_A11,
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GPIO_FMC_SDCKE0_1, GPIO_FMC_SDNE0_3, GPIO_FMC_SDNWE_3, GPIO_FMC_NBL0,
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GPIO_FMC_SDNRAS, GPIO_FMC_NBL1, GPIO_FMC_BA0, GPIO_FMC_BA1,
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GPIO_FMC_SDCLK, GPIO_FMC_SDNCAS
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};
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static const uint32_t g_dataconfig[STM32_FMC_NDATACONFIGS] =
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{
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GPIO_FMC_D0, GPIO_FMC_D1, GPIO_FMC_D2, GPIO_FMC_D3, GPIO_FMC_D4,
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GPIO_FMC_D5, GPIO_FMC_D6, GPIO_FMC_D7, GPIO_FMC_D8, GPIO_FMC_D9,
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GPIO_FMC_D10, GPIO_FMC_D11, GPIO_FMC_D12, GPIO_FMC_D13, GPIO_FMC_D14,
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GPIO_FMC_D15
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};
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: stm32_extmemgpios
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*
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* Description:
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* Initialize GPIOs for external memory usage
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*
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****************************************************************************/
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static void stm32_extmemgpios(const uint32_t *gpios, int ngpios)
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{
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int i;
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/* Configure GPIOs */
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for (i = 0; i < ngpios; i++)
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{
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stm32_configgpio(gpios[i]);
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}
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}
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/****************************************************************************
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* Name: stm32_sdramcommand
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*
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* Description:
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* Initialize data line GPIOs for external memory access
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*
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****************************************************************************/
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static void stm32_sdramcommand(uint32_t command)
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{
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uint32_t regval;
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volatile uint32_t timeout = 0xffff;
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regval = getreg32(STM32_FMC_SDSR) & 0x00000020;
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while ((regval != 0) && timeout-- > 0)
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{
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regval = getreg32(STM32_FMC_SDSR) & 0x00000020;
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}
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putreg32(command, STM32_FMC_SDCMR);
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timeout = 0xffff;
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regval = getreg32(STM32_FMC_SDSR) & 0x00000020;
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while ((regval != 0) && timeout-- > 0)
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{
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regval = getreg32(STM32_FMC_SDSR) & 0x00000020;
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}
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}
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/****************************************************************************
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* Name: stm32_enablefmc
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*
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* Description:
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* enable clocking to the FMC module
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*
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****************************************************************************/
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void stm32_enablefmc(void)
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{
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uint32_t regval;
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volatile int count;
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/* Enable GPIOs as FMC / memory pins */
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stm32_extmemgpios(g_addressconfig, STM32_FMC_NADDRCONFIGS);
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stm32_extmemgpios(g_dataconfig, STM32_FMC_NDATACONFIGS);
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/* Enable AHB clocking to the FMC */
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regval = getreg32(STM32_RCC_AHB3ENR);
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regval |= RCC_AHB3ENR_FMCEN;
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putreg32(regval, STM32_RCC_AHB3ENR);
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/* Configure and enable the SDRAM bank1
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*
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* FMC clock = 216MHz/2 = 108MHz
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* 108MHz = 9,26 ns
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* All timings from the datasheet for Speedgrade -6A (=6ns)
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*/
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putreg32(FMC_SDCR_RPIPE_0 |
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FMC_SDCR_BURST_READ |
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FMC_SDCR_SDCLK_2X |
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FMC_SDCR_CASLAT_3 |
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FMC_SDCR_BANKS_4 |
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FMC_SDCR_WIDTH_16 |
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FMC_SDCR_ROWBITS_12 |
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FMC_SDCR_COLBITS_8,
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STM32_FMC_SDCR1);
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putreg32(FMC_SDTR_TRCD(2) | /* tRCD min = 18ns */
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FMC_SDTR_TRP(2) | /* tRP min = 18ns */
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FMC_SDTR_TWR(2) | /* tWR = 2CLK */
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FMC_SDTR_TRC(7) | /* tRC min = 64ns */
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FMC_SDTR_TRAS(5) | /* tRAS min = 46ns */
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FMC_SDTR_TXSR(8) | /* tXSR min = 74ns */
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FMC_SDTR_TMRD(2), /* tMRD = 2CLK */
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STM32_FMC_SDTR1);
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/* SDRAM Initialization sequence */
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stm32_sdramcommand(STM32_SDRAM_CLKEN); /* Clock enable command */
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for (count = 0; count < 10000; count++) ; /* Delay */
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stm32_sdramcommand(STM32_SDRAM_PALL); /* Precharge ALL command */
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stm32_sdramcommand(STM32_SDRAM_REFRESH); /* Auto refresh command */
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stm32_sdramcommand(STM32_SDRAM_MODEREG); /* Mode Register program */
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/* Set refresh count
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*
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* FMC_CLK = 108MHz
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* Refresh_Rate = 64ms / 4096 rows = 15.63us
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* Counter = (FMC_CLK * Refresh_Rate) - 20
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*/
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putreg32(1668 << 1, STM32_FMC_SDRTR);
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}
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/****************************************************************************
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* Name: stm32_disablefmc
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*
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* Description:
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* enable clocking to the FMC module
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*
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****************************************************************************/
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void stm32_disablefmc(void)
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{
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uint32_t regval;
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/* Disable AHB clocking to the FMC */
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regval = getreg32(STM32_RCC_AHB3ENR);
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regval &= ~(uint32_t)RCC_AHB3ENR_FMCEN;
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putreg32(regval, STM32_RCC_AHB3ENR);
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}
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