e8e2a0875a
Alan Carvalho de Assis has submitted the ICL and we can migrate the licenses to Apache. Gregory Nutt has submitted the SGA and we can migrate the licenses to Apache. Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
135 lines
4.5 KiB
Plaintext
135 lines
4.5 KiB
Plaintext
/****************************************************************************
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* boards/arm/lpc43xx/bambino-200e/scripts/spificonfig.ld
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/*
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* Power-Up Reset Overview
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* -----------------------
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*
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* The ARM core starts executing code on reset with the program counter set
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* to 0x0000 0000. The LPC43xx contains a shadow pointer register that
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* allows areas of memory to be mapped to address 0x0000 0000. The default,
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* reset value of the shadow pointer is 0x1040 0000 so that on reset code in
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* the boot ROM is always executed first.
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*
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* The boot starts after reset is released. The IRC is selected as CPU clock
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* and the Cortex-M4 starts the boot loader. By default the JTAG access to the
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* chip is disabled at reset. The boot ROM determines the boot mode based on
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* the OTP BOOT_SRC value or reset state pins. For flash-based parts, the part
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* boots from internal flash by default. Otherwise, the boot ROM copies the
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* image to internal SRAM at location 0x1000 0000, sets the ARM's shadow
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* pointer to 0x1000 0000, and jumps to that location.
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*
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* Of course, using JTAG the executable image can be also loaded directly
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* into and executed from SRAM.
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*/
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/* The LPC4330 on the LPC4330-Xplorer has the following memory resources:
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*
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* 1. 4096Kb of SPIFI FLASH beginning at address 0x1400:0000
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* 2. 264KB of total SRAM:
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* a. 128KB of SRAM in the CPU block beginning at address 0x1000:0000
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* b. 72KB beginning at address 0x1008:0000 and
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* c. 64KB of AHB SRAM in three banks beginning at addresses 0x2000:0000,
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* 0x2000:8000 and 0x2000:C000.
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* 3. No internal FLASH
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*
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* Here we assume that:
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*
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* 1. We will be running out of SPIFI flash at 0x1400:0000, and
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* 2. All .data and .bss will all fit into the 128KB CPU SRAM block.
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*/
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MEMORY
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{
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progmem (rx) : ORIGIN = 0x14000000, LENGTH = 1024K
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datamem (rwx) : ORIGIN = 0x10000000, LENGTH = 128K
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}
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OUTPUT_ARCH(arm)
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ENTRY(__start) /* Treat __start as the anchor for dead code stripping */
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EXTERN(_vectors) /* Force the vectors to be included in the output */
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SECTIONS
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{
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.text : {
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_stext = ABSOLUTE(.);
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*(.vectors)
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*(.text .text.*)
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*(.fixup)
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*(.gnu.warning)
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*(.rodata .rodata.*)
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*(.gnu.linkonce.t.*)
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*(.glue_7)
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*(.glue_7t)
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*(.got)
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*(.gcc_except_table)
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*(.gnu.linkonce.r.*)
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_etext = ABSOLUTE(.);
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} > progmem
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.init_section : {
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_sinit = ABSOLUTE(.);
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*(.init_array .init_array.*)
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_einit = ABSOLUTE(.);
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} > progmem
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.ARM.extab : {
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*(.ARM.extab*)
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} > progmem
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__exidx_start = ABSOLUTE(.);
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.ARM.exidx : {
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*(.ARM.exidx*)
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} > progmem
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__exidx_end = ABSOLUTE(.);
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_eronly = ABSOLUTE(.);
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.data : {
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_sdata = ABSOLUTE(.);
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*(.data .data.*)
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*(.gnu.linkonce.d.*)
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CONSTRUCTORS
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. = ALIGN(4);
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_edata = ABSOLUTE(.);
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} > datamem AT > progmem
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.bss : { /* BSS */
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_sbss = ABSOLUTE(.);
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*(.bss .bss.*)
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*(.gnu.linkonce.b.*)
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*(COMMON)
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. = ALIGN(4);
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_ebss = ABSOLUTE(.);
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} > datamem
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/* Stabs debugging sections. */
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.stab 0 : { *(.stab) }
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.stabstr 0 : { *(.stabstr) }
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.stab.excl 0 : { *(.stab.excl) }
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.stab.exclstr 0 : { *(.stab.exclstr) }
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.stab.index 0 : { *(.stab.index) }
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.stab.indexstr 0 : { *(.stab.indexstr) }
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.comment 0 : { *(.comment) }
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.debug_abbrev 0 : { *(.debug_abbrev) }
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.debug_info 0 : { *(.debug_info) }
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.debug_line 0 : { *(.debug_line) }
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.debug_pubnames 0 : { *(.debug_pubnames) }
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.debug_aranges 0 : { *(.debug_aranges) }
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}
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