50321df42d
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5146 42af7a65-404d-4744-a932-0658087f49c3
103 lines
5.4 KiB
C
103 lines
5.4 KiB
C
/************************************************************************************
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* arch/hc/src/m9s12/chip.h
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*
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* Copyright (C) 2009-2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_HC_SRC_M9S12_CHIP_H
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#define __ARCH_HC_SRC_M9S12_CHIP_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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/************************************************************************************
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* Definitions
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************************************************************************************/
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/* Memory Map.
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*
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* At reset:
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* 0x0000<30>0x03ff: register space
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* 0x0000<30>0x1fff: 7K RAM (1K RAM hidden behind register space)
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*/
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#define HCS12_REG_BASE 0x0000 /* 0x0000-0x03ff: Mapped Register base address */
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#define HCS12_EEPROM_BASE 0x0800 /* 0x0800: Mapped EEPROM base address */
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#define HCS12_SRAM_BASE 0x2000 /* 0x2000-0x3fff: Mapped SRAM base address */
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#define HCS12_FFLASH1_BASE 0x4000 /* 0x4000-0x7fff: 16Kb Fixed FLASH EEPROM */
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#define HCS12_PPAGE_BASE 0x8000 /* 0x8000-0xbfff: 16Kb Page window */
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#define HCS12_FFLASH2_BASE 0xc000 /* 0xc000-0xffff: 16Kb Fixed FLASH EEPROM */
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/* Device Register Map Overview (all relative to HCS12_REG_BASE) */
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#define HCS12_CORE1_BASE 0x0000 /* 0x0000<30>0x0017: Ports A, B, E, Modes, Inits (MMC, INT, MEBI) */
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/* 0x0018<31>0x0019: Reserved */
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#define HCS12_DEVID_BASE 0x001a /* 0x001a-0x001b: Device ID register (PARTID) */
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#define HCS12_CORE2_BASE 0x001c /* 0x001c<31>0x001f: MEMSIZ, IRQ, HPRIO (INT, MMC) */
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#define HCS12_CORE3_BASE 0x0020 /* 0x0020-0x002f: DBG */
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#define HCS12_CORE4_BASE 0x0030 /* 0x0030<33>0x0033: PPAGE, Port K (MEBI, MMC) */
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#define HCS12_CRG_BASE 0x0034 /* 0x0034<33>0x003f: Clock and Reset Generator (PLL, RTI, COP) */
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#define HCS12_TIM_BASE 0x0040 /* 0x0040<34>0x006f: Standard Timer 16-bit 4 channels (TIM) */
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/* 0x0070<37>0x007f: Reserved */
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#define HCS12_ATD_BASE 0x0080 /* 0x0080<38>0x009f: Analog-to-Digital Converter 10-bit, 8-channel (ATD) */
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/* 0x00a0<61>0x00c7: Reserved */
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#define HCS12_SCI0_BASE 0x00c8 /* 0x00c8<63>0x00cf: Serial Communications Interface 0 (SCI0) */
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#define HCS12_SCI1_BASE 0x00d0 /* 0x00d0<64>0x00d7: Serial Communications Interface 1 (SCI1) */o
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#define HCS12_SPI_BASE 0x00d8 /* 0x00d8<64>0x00df: Serial Peripheral Interface (SPI) */
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#define HCS12_IIC_BASE 0x00e0 /* 0x00e0<65>0x00e7: Inter IC Bus (IIC) */
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/* 0x00e8<65>0x00ff: Reserved */
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#define HCS12_FLASH_BASE 0x0100 /* 0x0100<30>0x010f: FLASH Control Register */
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/* 0x0110<31>0x011f: Reserved */
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#define HCS12_EPHY_BASE 0x0120 /* 0x0120<32>0x0123: Ethernet Physical Interface (EPHY) */
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/* 0x0124<32>0x013f: Reserved */
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#define HCS12_EMAC_BASE 0x0140 /* 0x0140<34>0x016f: Ethernet Media Access Controller (EMAC) */
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/* 0x0170<37>0x023f: Reserved */
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#define HCS12_PIM_BASE 0x0240 /* 0x0240<34>0x026f: Port Integration Module (PIM) */
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/* 0x0270<37>0x03ff: Reserved */
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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#endif /* __ARCH_HC_SRC_M9S12_CHIP_H */
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