119 lines
4.3 KiB
ArmAsm
119 lines
4.3 KiB
ArmAsm
/****************************************************************************
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* arch/mips/src/mips32/up_syscall0.S
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*
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* Copyright (C) 2011, 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <arch/mips32/registers.h>
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#include <arch/mips32/cp0.h>
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/****************************************************************************
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* Public Symbols
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****************************************************************************/
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.file "up_syscall0.S"
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.global sys_call0
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.global sys_call1
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.global sys_call2
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.global sys_call3
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: up_syscall0, up_syscall1, up_syscall2, up_syscall3
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*
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* Description:
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* up_syscall0 - System call SYS_ argument and no additional parameters.
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* up_syscall1 - System call SYS_ argument and one additional parameter.
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* up_syscall2 - System call SYS_ argument and two additional parameters.
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* up_syscall3 - System call SYS_ argument and three additional parameters.
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*
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* Assumption:
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* All interrupts are disabled except for the software interrupts.
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*
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****************************************************************************/
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.text
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.set noreorder
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.set nomips16
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#ifdef CONFIG_MIPS_MICROMIPS
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.set micromips
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#endif
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.ent sys_call0
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sys_call0: /* r4 holds the syscall number */
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sys_call1: /* r4 holds the syscall number, argument in r5 */
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sys_call2: /* r4 holds the syscall number, arguments in r5 and r6 */
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sys_call3: /* r4 holds the syscall number, arguments in r5, r6, and r7 */
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.set push
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.set noat
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/* Set Bit 8 to request the software interrupt */
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mfc0 t3, MIPS32_CP0_CAUSE /* t3 = CP0 cause register */
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ori t3, (1 << 8) /* Bit 8: Request software interrupt 0 */
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.set noreorder
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mtc0 t3, MIPS32_CP0_CAUSE /* Trigger the software interrupt */
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/* The actual interrupt will not a occur for a few more cycles. Let's
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* put a few nop's here in hope that the SW interrupt occurs during
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* the sequence of nops.
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*/
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nop
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nop
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nop
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nop
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/* Then return with the result of the software interrupt in v0 */
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j ra
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nop
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.end sys_call0
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