235 lines
12 KiB
C
235 lines
12 KiB
C
/****************************************************************************
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* arch/arm/src/stm32/hardware/stm32f40xxx_uart.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F40XXX_UART_H
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#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F40XXX_UART_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Register Offsets *********************************************************/
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#define STM32_USART_SR_OFFSET 0x0000 /* Status register (32-bits) */
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#define STM32_USART_DR_OFFSET 0x0004 /* Data register (32-bits) */
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#define STM32_USART_BRR_OFFSET 0x0008 /* Baud Rate Register (32-bits) */
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#define STM32_USART_CR1_OFFSET 0x000c /* Control register 1 (32-bits) */
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#define STM32_USART_CR2_OFFSET 0x0010 /* Control register 2 (32-bits) */
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#define STM32_USART_CR3_OFFSET 0x0014 /* Control register 3 (32-bits) */
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#define STM32_USART_GTPR_OFFSET 0x0018 /* Guard time and prescaler register (32-bits) */
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/* Register Addresses *******************************************************/
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#if STM32_NUSART > 0
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# define STM32_USART1_SR (STM32_USART1_BASE+STM32_USART_SR_OFFSET)
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# define STM32_USART1_DR (STM32_USART1_BASE+STM32_USART_DR_OFFSET)
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# define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET)
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# define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET)
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# define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET)
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# define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET)
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# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET)
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#endif
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#if STM32_NUSART > 1
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# define STM32_USART2_SR (STM32_USART2_BASE+STM32_USART_SR_OFFSET)
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# define STM32_USART2_DR (STM32_USART2_BASE+STM32_USART_DR_OFFSET)
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# define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET)
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# define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET)
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# define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET)
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# define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET)
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# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET)
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#endif
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#if STM32_NUSART > 2
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# define STM32_USART3_SR (STM32_USART3_BASE+STM32_USART_SR_OFFSET)
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# define STM32_USART3_DR (STM32_USART3_BASE+STM32_USART_DR_OFFSET)
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# define STM32_USART3_BRR (STM32_USART3_BASE+STM32_USART_BRR_OFFSET)
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# define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET)
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# define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET)
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# define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET)
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# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET)
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#endif
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#if STM32_NUSART > 3
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# define STM32_UART4_SR (STM32_UART4_BASE+STM32_USART_SR_OFFSET)
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# define STM32_UART4_DR (STM32_UART4_BASE+STM32_USART_DR_OFFSET)
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# define STM32_UART4_BRR (STM32_UART4_BASE+STM32_USART_BRR_OFFSET)
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# define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET)
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# define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET)
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# define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET)
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#endif
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#if STM32_NUSART > 4
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# define STM32_UART5_SR (STM32_UART5_BASE+STM32_USART_SR_OFFSET)
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# define STM32_UART5_DR (STM32_UART5_BASE+STM32_USART_DR_OFFSET)
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# define STM32_UART5_BRR (STM32_UART5_BASE+STM32_USART_BRR_OFFSET)
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# define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET)
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# define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET)
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# define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET)
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#endif
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#if STM32_NUSART > 5
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# define STM32_USART6_SR (STM32_USART6_BASE+STM32_USART_SR_OFFSET)
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# define STM32_USART6_DR (STM32_USART6_BASE+STM32_USART_DR_OFFSET)
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# define STM32_USART6_BRR (STM32_USART6_BASE+STM32_USART_BRR_OFFSET)
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# define STM32_USART6_CR1 (STM32_USART6_BASE+STM32_USART_CR1_OFFSET)
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# define STM32_USART6_CR2 (STM32_USART6_BASE+STM32_USART_CR2_OFFSET)
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# define STM32_USART6_CR3 (STM32_USART6_BASE+STM32_USART_CR3_OFFSET)
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# define STM32_USART6_GTPR (STM32_USART6_BASE+STM32_USART_GTPR_OFFSET)
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#endif
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#if STM32_NUSART > 6
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# define STM32_UART7_SR (STM32_UART7_BASE+STM32_USART_SR_OFFSET)
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# define STM32_UART7_DR (STM32_UART7_BASE+STM32_USART_DR_OFFSET)
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# define STM32_UART7_BRR (STM32_UART7_BASE+STM32_USART_BRR_OFFSET)
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# define STM32_UART7_CR1 (STM32_UART7_BASE+STM32_USART_CR1_OFFSET)
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# define STM32_UART7_CR2 (STM32_UART7_BASE+STM32_USART_CR2_OFFSET)
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# define STM32_UART7_CR3 (STM32_UART7_BASE+STM32_USART_CR3_OFFSET)
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#endif
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#if STM32_NUSART > 7
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# define STM32_UART8_SR (STM32_UART8_BASE+STM32_USART_SR_OFFSET)
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# define STM32_UART8_DR (STM32_UART8_BASE+STM32_USART_DR_OFFSET)
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# define STM32_UART8_BRR (STM32_UART8_BASE+STM32_USART_BRR_OFFSET)
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# define STM32_UART8_CR1 (STM32_UART8_BASE+STM32_USART_CR1_OFFSET)
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# define STM32_UART8_CR2 (STM32_UART8_BASE+STM32_USART_CR2_OFFSET)
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# define STM32_UART8_CR3 (STM32_UART8_BASE+STM32_USART_CR3_OFFSET)
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#endif
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/* Register Bitfield Definitions ********************************************/
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/* Status register */
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#define USART_SR_PE (1 << 0) /* Bit 0: Parity Error */
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#define USART_SR_FE (1 << 1) /* Bit 1: Framing Error */
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#define USART_SR_NE (1 << 2) /* Bit 2: Noise Error Flag */
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#define USART_SR_ORE (1 << 3) /* Bit 3: OverRun Error */
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#define USART_SR_IDLE (1 << 4) /* Bit 4: IDLE line detected */
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#define USART_SR_RXNE (1 << 5) /* Bit 5: Read Data Register Not Empty */
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#define USART_SR_TC (1 << 6) /* Bit 6: Transmission Complete */
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#define USART_SR_TXE (1 << 7) /* Bit 7: Transmit Data Register Empty */
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#define USART_SR_LBD (1 << 8) /* Bit 8: LIN Break Detection Flag */
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#define USART_SR_CTS (1 << 9) /* Bit 9: CTS Flag */
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#define USART_SR_ALLBITS (0x03ff)
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#define USART_SR_CLRBITS (USART_SR_CTS|USART_SR_LBD) /* Cleared by SW write to SR */
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/* Data register */
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#define USART_DR_SHIFT (0) /* Bits 8:0: Data value */
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#define USART_DR_MASK (0xff << USART_DR_SHIFT)
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/* Baud Rate Register */
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#define USART_BRR_FRAC_SHIFT (0) /* Bits 3-0: fraction of USARTDIV */
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#define USART_BRR_FRAC_MASK (0x0f << USART_BRR_FRAC_SHIFT)
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#define USART_BRR_MANT_SHIFT (4) /* Bits 15-4: mantissa of USARTDIV */
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#define USART_BRR_MANT_MASK (0x0fff << USART_BRR_MANT_SHIFT)
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/* Control register 1 */
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#define USART_CR1_SBK (1 << 0) /* Bit 0: Send Break */
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#define USART_CR1_RWU (1 << 1) /* Bit 1: Receiver wakeup */
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#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */
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#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */
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#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */
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#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */
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#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */
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#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */
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#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */
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#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */
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#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */
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#define USART_CR1_WAKE (1 << 11) /* Bit 11: Wakeup method */
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#define USART_CR1_M (1 << 12) /* Bit 12: word length */
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#define USART_CR1_UE (1 << 13) /* Bit 13: USART Enable */
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#define USART_CR1_OVER8 (1 << 15) /* Bit 15: Oversampling mode */
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#define USART_CR1_ALLINTS (USART_CR1_IDLEIE|USART_CR1_RXNEIE|USART_CR1_TCIE|USART_CR1_PEIE)
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/* Control register 2 */
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#define USART_CR2_ADD_SHIFT (0) /* Bits 3-0: Address of the USART node */
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#define USART_CR2_ADD_MASK (0x0f << USART_CR2_ADD_SHIFT)
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#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */
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#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */
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#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */
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#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */
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#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */
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#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */
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#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */
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#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT)
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# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */
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# define USART_CR2_STOP0p5 (1 << USART_CR2_STOP_SHIFT) /* 01: 0.5 Stop bit */
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# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */
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# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */
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#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */
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/* Control register 3 */
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#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */
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#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */
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#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */
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#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */
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#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */
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#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */
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#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */
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#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */
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#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */
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#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */
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#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */
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#define USART_CR3_ONEBIT (1 << 11) /* Bit 11: One sample bit method enable */
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/* Guard time and prescaler register */
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#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */
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#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT)
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#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */
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#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT)
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/* Compatibility definitions ************************************************/
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/* F3 Transmit/Read registers */
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#define STM32_USART_RDR_OFFSET STM32_USART_DR_OFFSET /* Receive data register */
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#define STM32_USART_TDR_OFFSET STM32_USART_DR_OFFSET /* Transmit data register */
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/****************************************************************************
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* Public Types
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****************************************************************************/
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Public Functions Prototypes
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****************************************************************************/
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#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F40XXX_UART_H */
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