295 lines
11 KiB
C
295 lines
11 KiB
C
/****************************************************************************
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* boards/arm/kinetis/teensy-3.x/include/board.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __BOARDS_ARM_KINETIS_TEENSY_3X_INCLUDE_BOARD_H
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#define __BOARDS_ARM_KINETIS_TEENSY_3X_INCLUDE_BOARD_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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# include <stdbool.h>
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Clocking *****************************************************************/
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/* The teensy-3.1 has a 16MHz crystal on board */
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#undef BOARD_EXTCLOCK /* Crystal */
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#define BOARD_EXTAL_LP /* Low Power, as opposed to Hi Gain */
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/* BOARD_FRDIV is MCG_C1_FRDIV_DIV512 from kinetis_mcg.h.
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* According to the k20 reference manual, when transitioning MCG clock modes
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* to FLL Bypassed External the C1 divider must be set so that the FLL clock
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* is between 31.25 and 39.0625 khz.
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* For teensy-3.x that works out to a divider of 512.
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*/
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#define BOARD_FRDIV MCG_C1_FRDIV_DIV512
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#define BOARD_EXTAL_FREQ 16000000 /* 16MHz crystal frequency (REFCLK) */
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#define BOARD_XTAL32_FREQ 32768 /* 32KHz RTC Oscillator (not populated) */
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/* PLL Configuration.
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* NOTE: Only even frequency crystals are supported that will produce a 2MHz
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* reference clock to the PLL.
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* The rated speed for the MK20DX256VLH7 is 72MHz and 50MHz for the
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* MK20DX128VLH5, but according to the PJRC website, both can be overclocked
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* at 96MHz
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*
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* MK20DX128VLH5 Rated Frequency 50MHz (selecting 48Mhz to use USB)
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*
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* PLL Input frequency: PLLIN = REFCLK/PRDIV = 16MHz/8 = 2MHz
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* PLL Output frequency: PLLOUT = PLLIN*VDIV = 2Mhz*24 = 48MHz
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* MCG Frequency: PLLOUT = 48MHz
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*
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* MK20DX256VLH7 Rated Frequency 72MHz
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*
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* PLL Input frequency: PLLIN = REFCLK/PRDIV = 16MHz/8 = 2MHz
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* PLL Output frequency: PLLOUT = PLLIN*VDIV = 2Mhz*36 = 72MHz
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* MCG Frequency: PLLOUT = 72MHz
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*
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* Board can be overclocked at 96MHz (per PJRC.com)
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* PLL Input frequency: PLLIN = REFCLK/PRDIV = 16MHz/8 = 2MHz
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* PLL Output frequency: PLLOUT = PLLIN*VDIV = MHz*48 = 96MHz
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* MCG Frequency: PLLOUT = 96MHz
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*/
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#if defined(CONFIG_TEENSY_3X_OVERCLOCK)
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/* PLL Configuration */
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# define BOARD_PRDIV 8 /* PLL External Reference Divider */
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# define BOARD_VDIV 48 /* PLL VCO Divider (frequency multiplier) */
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/* SIM CLKDIV1 dividers */
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# define BOARD_OUTDIV1 1 /* Core = MCG, 96MHz */
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# define BOARD_OUTDIV2 2 /* Bus = MCG/2, 48MHz */
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# define BOARD_OUTDIV3 0 /* N/A = No OUTDIV3 */
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# define BOARD_OUTDIV4 4 /* Flash clock = MCG/4, 24MHz */
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#elif defined(CONFIG_ARCH_CHIP_MK20DX256VLH7)
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/* PLL Configuration */
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# define BOARD_PRDIV 8 /* PLL External Reference Divider */
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# define BOARD_VDIV 36 /* PLL VCO Divider (frequency multiplier) */
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/* SIM CLKDIV1 dividers */
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# define BOARD_OUTDIV1 1 /* Core = MCG, 72MHz */
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# define BOARD_OUTDIV2 2 /* Bus = MCG/2, 36MHz */
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# define BOARD_OUTDIV3 0 /* N/A = No OUTDIV3 */
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# define BOARD_OUTDIV4 3 /* Flash clock = MCG/3, 72MHz */
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#elif defined(CONFIG_ARCH_CHIP_MK20DX128VLH5)
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/* PLL Configuration */
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# define BOARD_PRDIV 8 /* PLL External Reference Divider */
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# define BOARD_VDIV 24 /* PLL VCO Divider (frequency multiplier) */
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/* SIM CLKDIV1 dividers */
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# define BOARD_OUTDIV1 1 /* Core = MCG, 48MHz */
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# define BOARD_OUTDIV2 1 /* Bus = MCG/1, 48MHz */
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# define BOARD_OUTDIV3 0 /* N/A = No OUTDIV3 */
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# define BOARD_OUTDIV4 2 /* Flash clock = MCG/2, 24MHz */
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#endif
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#define BOARD_PLLIN_FREQ (BOARD_EXTAL_FREQ / BOARD_PRDIV)
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#define BOARD_PLLOUT_FREQ (BOARD_PLLIN_FREQ * BOARD_VDIV)
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#define BOARD_MCG_FREQ BOARD_PLLOUT_FREQ
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#define BOARD_CORECLK_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV1)
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#define BOARD_BUS_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV2)
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#define BOARD_FLEXBUS_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV3)
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#define BOARD_FLASHCLK_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV4)
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/* Use MCGPLLCLK as the output SIM_SOPT2 MUX selected by
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* SIM_SOPT2[PLLFLLSEL]
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*/
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#define BOARD_SOPT2_PLLFLLSEL SIM_SOPT2_PLLFLLSEL_MCGPLLCLK
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#define BOARD_SOPT2_FREQ BOARD_MCG_FREQ
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/* Divider output clock = Divider input clock ×
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* [ (USBFRAC+1) / (USBDIV+1) ]
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* SIM_CLKDIV2_FREQ = BOARD_SOPT2_FREQ ×
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* [ (USBFRAC+1) / (USBDIV+1) ]
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*/
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#if BOARD_SOPT2_FREQ == 96000000
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/* USBFRAC/USBDIV = 1/2 of 96Mhz clock = 48MHz */
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# define BOARD_SIM_CLKDIV2_USBFRAC 1
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# define BOARD_SIM_CLKDIV2_USBDIV 2
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#elif BOARD_SOPT2_FREQ == 72000000
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/* USBFRAC/USBDIV = 2/3 of 72Mhz clock = 48MHz */
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# define BOARD_SIM_CLKDIV2_USBFRAC 2
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# define BOARD_SIM_CLKDIV2_USBDIV 3
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#elif BOARD_SOPT2_FREQ == 48000000
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/* USBFRAC/USBDIV = 1/1 of 48Mhz clock = 48MHz */
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# define BOARD_SIM_CLKDIV2_USBFRAC 1
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# define BOARD_SIM_CLKDIV2_USBDIV 1
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#endif
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#define BOARD_SIM_CLKDIV2_FREQ (BOARD_SOPT2_FREQ / \
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BOARD_SIM_CLKDIV2_USBDIV * \
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BOARD_SIM_CLKDIV2_USBFRAC)
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/* Use the output of SIM_SOPT2[PLLFLLSEL] as the USB clock source */
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#define BOARD_USB_CLKSRC SIM_SOPT2_USBSRC
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#define BOARD_USB_FREQ BOARD_SIM_CLKDIV2_FREQ
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/* Allow USBOTG-FS Controller to Read from FLASH */
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#define BOARD_USB_FLASHACCESS
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/* PWM Configuration */
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/* FTM0 Channels */
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#define GPIO_FTM0_CH0OUT PIN_FTM0_CH0_2 /* Pin 22: PTC1 */
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#define GPIO_FTM0_CH1OUT PIN_FTM0_CH1_2 /* Pin 23: PTC2 */
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#define GPIO_FTM0_CH2OUT PIN_FTM0_CH2_2 /* Pin 9: PTC3 */
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#define GPIO_FTM0_CH3OUT PIN_FTM0_CH3 /* Pin 10: PTC4 */
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#define GPIO_FTM0_CH4OUT PIN_FTM0_CH4 /* Pin 6: PTD4 */
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#define GPIO_FTM0_CH5OUT PIN_FTM0_CH5_2 /* Pin 20: PTD5 */
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#define GPIO_FTM0_CH6OUT PIN_FTM0_CH6_2 /* Pin 21: PTD6 */
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#define GPIO_FTM0_CH7OUT PIN_FTM0_CH7_2 /* Pin 5: PTD7 */
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/* FTM1 Channels */
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#define GPIO_FTM1_CH0OUT PIN_FTM1_CH0_1 /* Pin 3: PTA12 */
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#define GPIO_FTM1_CH1OUT PIN_FTM1_CH1_1 /* Pin 4: PTA13 */
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/* FTM2 Channels */
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#define GPIO_FTM2_CH0OUT PIN_FTM2_CH0 /* Pin 25: PTB18 */
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#define GPIO_FTM2_CH1OUT PIN_FTM2_CH1 /* Pin 32: PTB19 */
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/* LED definitions **********************************************************/
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/* A single LED is available driven by PTC5.
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* The LED is grounded so bringing PTC5 high will illuminate the LED.
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*/
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/* LED index values for use with board_userled() */
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#define BOARD_LED 0
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#define BOARD_NLEDS 1
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/* LED bits for use with board_userled_all() */
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#define BOARD_LED_BIT (1 << BOARD_LED)
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/* When CONFIG_ARCH_LEDS is defined in the NuttX configuration, NuttX will
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* control the LED as defined below.
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* Thus if the LED is statically on, NuttX has successfully booted and is,
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* apparently, running normally.
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* If the LED is flashing at approximately 2Hz, then a fatal error has been
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* detected and the system has halted.
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*/
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#define LED_STARTED 0 /* STATUS LED=OFF */
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#define LED_HEAPALLOCATE 0 /* STATUS LED=OFF */
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#define LED_IRQSENABLED 0 /* STATUS LED=OFF */
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#define LED_STACKCREATED 1 /* STATUS LED=ON */
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#define LED_INIRQ 2 /* STATUS LED=no change */
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#define LED_SIGNAL 2 /* STATUS LED=no change */
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#define LED_ASSERTION 3 /* STATUS LED=no change */
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#define LED_PANIC 3 /* STATUS LED=flashing */
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/* Button definitions *******************************************************/
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/* The teensy-3.1 board has no standard GPIO contact buttons */
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/* Alternative pin resolution ***********************************************/
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/* The K20 has three UARTs with pin availability as follows:
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*
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* --------- ------ ----------- -------------------------
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* UART PORT BOARD PJRC PINOUT DESCRIPTION
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* FUNCTION LABEL
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* --------- ------ ----------- -------------------------
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* UART0_RX PTA1 (See above) MINI54TAN / Bootloader
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* PTB16 Pin 0 RX1 / Touch
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* PTD6 Pin 21 / A7 RX1 / CS / PWM
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* UART0_TX PTA2 (See above) MINI54TAN / Bootloader
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* PTB17 Pin 1 TX1 / Touch
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* PTD7 Pin 5 TX1 / PWM
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* --------- ------ ----------- -------------------------
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* UART1_RX PTC3 Pin 9 RX2 / CS / PWM
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* PTE1 Pad 26 (Pad on back of board)
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* UART1_TX PTC4 Pin 10 TX2 / CS / PWM
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* PTE0 Pad 31 (Pad on back of board)
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* --------- ------ ----------- -------------------------
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* UART2_RX PTD2 Pin 7 RX3 / DOUT
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* UART2_TX PTD3 Pin 8 TX3 / DIN
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* --------- ------ ----------- -------------------------
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*
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* The default serial console is UART0 on pins 0 (RX) and 1 (TX).
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*/
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#ifdef CONFIG_KINETIS_UART0
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# define PIN_UART0_RX PIN_UART0_RX_2
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# define PIN_UART0_TX PIN_UART0_TX_2
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#endif
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#ifdef CONFIG_KINETIS_UART1
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# define PIN_UART0_RX PIN_UART1_RX_1
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# define PIN_UART0_TX PIN_UART1_TX_1
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#endif
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#ifdef CONFIG_KINETIS_I2C0
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#ifdef CONFIG_TEENSY_3X_I2C_ALT_PINS
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# define PIN_I2C0_SCL (PIN_I2C0_SCL_1 | PIN_ALT2_OPENDRAIN | PIN_ALT2_SLOW)
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# define PIN_I2C0_SDA (PIN_I2C0_SDA_1 | PIN_ALT2_OPENDRAIN | PIN_ALT2_SLOW)
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#else
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# define PIN_I2C0_SCL (PIN_I2C0_SCL_2 | PIN_ALT2_OPENDRAIN | PIN_ALT2_SLOW)
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# define PIN_I2C0_SDA (PIN_I2C0_SDA_2 | PIN_ALT2_OPENDRAIN | PIN_ALT2_SLOW)
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#endif
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#endif
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/* REVISIT: Added only for clean compilation with I2C1 enabled. */
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#ifdef CONFIG_KINETIS_I2C1
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#ifdef CONFIG_TEENSY_3X_I2C_ALT_PINS
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# define PIN_I2C1_SCL (PIN_I2C1_SCL_1 | PIN_ALT2_OPENDRAIN | PIN_ALT2_SLOW)
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# define PIN_I2C1_SDA (PIN_I2C1_SDA_1 | PIN_ALT2_OPENDRAIN | PIN_ALT2_SLOW)
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#else
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# define PIN_I2C1_SCL (PIN_I2C1_SCL_2 | PIN_ALT2_OPENDRAIN | PIN_ALT2_SLOW)
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# define PIN_I2C1_SDA (PIN_I2C1_SDA_2 | PIN_ALT2_OPENDRAIN | PIN_ALT2_SLOW)
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#endif
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#endif
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#endif /* __BOARDS_ARM_KINETIS_TEENSY_3X_INCLUDE_BOARD_H */
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