7a8e9581ca
HiFive1 with qemu
* arch: risc-v: Add include/.gitignore
* arch: risc-v: Add src/.gitignore
* arch: risc-v: Remove uncommon function prototypes in include/irq.h
* arch: risc-v: Add missing symbols and function prototypes in src/common/up_internal.h
* arch: risc-v: Add src/common/up_modifyreg32.c
* arch: risc-v: Enable include Make.dep in src/Makefile
* arch: risc-v: Fix stack coloration in common/up_createstack.c
* arch: risc-v: Add common/up_puts.c
* arch: risc-v: Add common/up_checkstack.c
* arch: rv32im: Move all logics from up_dumpstate.c to up_assert.c
This change is same as other architectures like arm/src/armv7-m
* arch: Select ARCH_HAVE_STACKCHECK for RISC-V in Kconfig
* arch: risc-v: Add SiFive fe310 processor
NOTE: Currently only tested with qemu
* boards: hifive1-revb: Add SiFive hifive1-revb board
NOTE: Currently only tested with qemu
* tools: Add fe310 processor to configure.sh
Approved-by: Alan Carvalho de Assis <acassis@gmail.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
119 lines
3.7 KiB
Plaintext
119 lines
3.7 KiB
Plaintext
/****************************************************************************
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* boards/risc-v/fe310/hifive1-revb/scripts/ld.script
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*
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* Copyright (C) 2019 Masayuki Ishikawa. All rights reserved.
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* Author: Masayuki Ishikawa <masayuki.ishikawa@gmail.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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MEMORY
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{
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flash (rx) : ORIGIN = 0x20400000, LENGTH = 4096K
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sram (rwx) : ORIGIN = 0x80000000, LENGTH = 16K
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}
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OUTPUT_ARCH("riscv")
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ENTRY(_stext)
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EXTERN(_vectors)
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SECTIONS
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{
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.text : {
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_stext = ABSOLUTE(.);
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*(.vectors)
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*(.text .text.*)
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*(.fixup)
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*(.gnu.warning)
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*(.rodata .rodata.*)
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*(.gnu.linkonce.t.*)
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*(.glue_7)
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*(.glue_7t)
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*(.got)
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*(.gcc_except_table)
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*(.gnu.linkonce.r.*)
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_etext = ABSOLUTE(.);
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} > flash
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.init_section : ALIGN(4) {
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_sinit = ABSOLUTE(.);
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KEEP(*(.init_array .init_array.*))
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_einit = ABSOLUTE(.);
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} > flash
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.ARM.extab : ALIGN(4) {
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*(.ARM.extab*)
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} > flash
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.ARM.exidx : ALIGN(4) {
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__exidx_start = ABSOLUTE(.);
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*(.ARM.exidx*)
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__exidx_end = ABSOLUTE(.);
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} > flash
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_eronly = ABSOLUTE(.);
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.data : ALIGN(4) {
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_sdata = ABSOLUTE(.);
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*(.data .data.*)
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*(.sdata .sdata.*)
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*(.gnu.linkonce.d.*)
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*(.gnu.linkonce.s.*)
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CONSTRUCTORS
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. = ALIGN(4);
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_edata = ABSOLUTE(.);
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} > sram AT > flash
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.bss : ALIGN(4) {
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_sbss = ABSOLUTE(.);
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*(.bss .bss.*)
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*(.sbss .sbss.*)
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*(.gnu.linkonce.b.*)
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*(.gnu.linkonce.sb.*)
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*(COMMON)
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. = ALIGN(4);
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_ebss = ABSOLUTE(.);
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} > sram
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/* Stabs debugging sections. */
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.stab 0 : { *(.stab) }
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.stabstr 0 : { *(.stabstr) }
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.stab.excl 0 : { *(.stab.excl) }
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.stab.exclstr 0 : { *(.stab.exclstr) }
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.stab.index 0 : { *(.stab.index) }
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.stab.indexstr 0 : { *(.stab.indexstr) }
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.comment 0 : { *(.comment) }
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.debug_abbrev 0 : { *(.debug_abbrev) }
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.debug_info 0 : { *(.debug_info) }
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.debug_line 0 : { *(.debug_line) }
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.debug_pubnames 0 : { *(.debug_pubnames) }
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.debug_aranges 0 : { *(.debug_aranges) }
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}
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