543 lines
13 KiB
C
543 lines
13 KiB
C
/****************************************************************************
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* boards/arm/stm32/nucleo-f302r8/src/stm32_highpri.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <inttypes.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <strings.h>
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#include <unistd.h>
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#include <debug.h>
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#include <nuttx/arch.h>
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#include <nuttx/signal.h>
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#include <nuttx/timers/pwm.h>
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#include <nuttx/analog/adc.h>
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#include <nuttx/analog/ioctl.h>
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#include <arch/irq.h>
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#include <arch/armv7-m/nvicpri.h>
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#include "arm_internal.h"
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#include "ram_vectors.h"
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#include "stm32_pwm.h"
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#include "stm32_adc.h"
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#include "stm32_dma.h"
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#include <arch/board/board.h>
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#ifdef CONFIG_NUCLEOF302R8_HIGHPRI
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Configuration ************************************************************/
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#ifndef CONFIG_ARCH_HIPRI_INTERRUPT
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# error CONFIG_ARCH_HIPRI_INTERRUPT is required
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#endif
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#ifndef CONFIG_ARCH_RAMVECTORS
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# error CONFIG_ARCH_RAMVECTORS is required
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#endif
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#ifndef CONFIG_ARCH_IRQPRIO
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# error CONFIG_ARCH_IRQPRIO is required
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#endif
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#ifndef CONFIG_ARCH_FPU
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# warning Set CONFIG_ARCH_FPU for hardware FPU support
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#endif
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#ifdef CONFIG_STM32_ADC1_DMA
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# if defined(CONFIG_STM32_TIM1_PWM)
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# define HIGHPRI_HAVE_TIM1
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# endif
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# if (CONFIG_STM32_ADC1_DMA_CFG != 1)
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# error ADC1 DMA must be configured in Circular Mode
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# endif
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# if !defined(HIGHPRI_HAVE_TIM1)
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# error "Needs TIM1 to trigger ADC DMA"
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# endif
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#endif
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#if (CONFIG_STM32_ADC1_INJECTED_CHAN > 0)
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# if (CONFIG_STM32_ADC1_INJECTED_CHAN > 2)
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# error Max 2 injected channels supported for now
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# else
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# define HIGHPRI_HAVE_INJECTED
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# endif
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#endif
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#ifdef HIGHPRI_HAVE_INJECTED
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# define INJ_NCHANNELS CONFIG_STM32_ADC1_INJECTED_CHAN
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#else
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# define INJ_NCHANNELS (0)
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#endif
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#ifndef CONFIG_STM32_ADC1_DMA
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# define REG_NCHANNELS (1)
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#else
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# define REG_NCHANNELS (3)
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#endif
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#define ADC1_NCHANNELS (REG_NCHANNELS + INJ_NCHANNELS)
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#define DEV1_PORT (1)
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#define DEV1_NCHANNELS ADC1_NCHANNELS
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#define ADC_REF_VOLTAGE (3.3f)
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#define ADC_VAL_MAX (4095)
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/****************************************************************************
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* Private Types
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****************************************************************************/
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/* High priority example private data */
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struct highpri_s
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{
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struct stm32_adc_dev_s *adc1;
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#ifdef HIGHPRI_HAVE_TIM1
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struct stm32_pwm_dev_s *pwm;
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#endif
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volatile uint32_t cntr1;
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volatile uint32_t cntr2;
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volatile uint8_t current;
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uint16_t r_val[REG_NCHANNELS];
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float r_volt[REG_NCHANNELS];
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#ifdef HIGHPRI_HAVE_INJECTED
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uint16_t j_val[INJ_NCHANNELS];
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float j_volt[INJ_NCHANNELS];
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#endif
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bool lock;
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};
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/* ADC channel list */
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static const uint8_t g_chanlist1[DEV1_NCHANNELS] =
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{
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1,
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#ifdef CONFIG_STM32_ADC1_DMA
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2,
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11,
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#endif
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#if INJ_NCHANNELS > 0
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7,
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#endif
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#if INJ_NCHANNELS > 1
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6
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#endif
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};
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/* Configurations of pins used by ADC channel */
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static const uint32_t g_pinlist1[DEV1_NCHANNELS] =
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{
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GPIO_ADC1_IN1, /* PA0/A0 */
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#ifdef CONFIG_STM32_ADC1_DMA
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GPIO_ADC1_IN2, /* PA1/A1 */
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GPIO_ADC1_IN11, /* PB0/A3 */
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#endif
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#if INJ_NCHANNELS > 0
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GPIO_ADC1_IN7, /* PC1/A4 */
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#endif
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#if INJ_NCHANNELS > 1
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GPIO_ADC1_IN6 /* PC0/A5 */
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#endif
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};
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static struct highpri_s g_highpri;
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: adc12_handler
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*
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* Description:
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* This is the handler for the high speed ADC interrupt.
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*
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****************************************************************************/
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#if !defined(CONFIG_STM32_ADC1_DMA) || defined(HIGHPRI_HAVE_INJECTED)
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void adc12_handler(void)
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{
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struct stm32_adc_dev_s *adc = g_highpri.adc1;
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float ref = ADC_REF_VOLTAGE;
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float bit = ADC_VAL_MAX;
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uint32_t pending;
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#ifdef HIGHPRI_HAVE_INJECTED
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int i = 0;
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#endif
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/* Get pending ADC interrupts */
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pending = STM32_ADC_INT_GET(adc);
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if (g_highpri.lock == true)
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{
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goto irq_out;
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}
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#ifndef CONFIG_STM32_ADC1_DMA
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/* Regular channel end of conversion */
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if (pending & ADC_ISR_EOC)
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{
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/* Increase regular sequence counter */
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g_highpri.cntr1 += 1;
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/* Get regular data */
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g_highpri.r_val[g_highpri.current] = STM32_ADC_REGDATA_GET(adc);
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/* Do some floating point operations */
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g_highpri.r_volt[g_highpri.current] =
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(float)g_highpri.r_val[g_highpri.current] * ref / bit;
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if (g_highpri.current >= REG_NCHANNELS - 1)
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{
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g_highpri.current = 0;
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}
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else
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{
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g_highpri.current += 1;
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}
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}
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#endif
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#ifdef HIGHPRI_HAVE_INJECTED
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/* Injected channel end of sequence */
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if (pending & ADC_ISR_JEOS)
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{
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/* Increase injected sequence counter */
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g_highpri.cntr2 += 1;
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/* Get injected channels */
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for (i = 0; i < INJ_NCHANNELS; i += 1)
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{
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g_highpri.j_val[i] = STM32_ADC_INJDATA_GET(adc, i);
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}
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/* Do some floating point operations */
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for (i = 0; i < INJ_NCHANNELS; i += 1)
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{
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g_highpri.j_volt[i] = (float)g_highpri.j_val[i] * ref / bit;
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}
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}
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#endif
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irq_out:
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/* Clear ADC pending interrupts */
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STM32_ADC_INT_ACK(adc, pending);
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}
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#endif
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/****************************************************************************
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* Name: dmach1_handler
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*
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* Description:
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* This is the handler for the high speed ADC interrupt using DMA transfer.
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*
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****************************************************************************/
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#ifdef CONFIG_STM32_ADC1_DMA
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void dma1ch1_handler(void)
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{
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float ref = ADC_REF_VOLTAGE;
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float bit = ADC_VAL_MAX;
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uint32_t pending;
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int i;
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pending = stm32_dma_intget(STM32_DMA1_CHAN1);
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if (g_highpri.lock == true)
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{
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goto irq_out;
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}
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/* Increase regular sequence counter */
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g_highpri.cntr1 += 1;
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for (i = 0; i < REG_NCHANNELS; i += 1)
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{
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/* Do some floating point operations */
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g_highpri.r_volt[i] = (float)g_highpri.r_val[i] * ref / bit;
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}
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irq_out:
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/* Clear DMA pending interrupts */
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stm32_dma_intack(STM32_DMA1_CHAN1, pending);
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}
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#endif
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: highpri_main
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*
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* Description:
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* Main entry point in into the high priority interrupt test.
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*
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****************************************************************************/
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int highpri_main(int argc, char *argv[])
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{
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#ifdef HIGHPRI_HAVE_TIM1
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struct stm32_pwm_dev_s *pwm1;
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#endif
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struct adc_dev_s *adc1;
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struct highpri_s *highpri;
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int ret;
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int i;
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highpri = &g_highpri;
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/* Initialize highpri structure */
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memset(highpri, 0, sizeof(struct highpri_s));
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printf("\nhighpri_main: Started\n");
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/* Configure the pins as analog inputs for the selected channels */
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for (i = 0; i < DEV1_NCHANNELS; i++)
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{
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stm32_configgpio(g_pinlist1[i]);
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}
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/* Initialize ADC driver */
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adc1 = stm32_adcinitialize(DEV1_PORT, g_chanlist1, DEV1_NCHANNELS);
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if (adc1 == NULL)
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{
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aerr("ERROR: Failed to get ADC interface 1\n");
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ret = EXIT_FAILURE;
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goto errout;
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}
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highpri->adc1 = (struct stm32_adc_dev_s *)adc1->ad_priv;
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#ifdef HIGHPRI_HAVE_TIM1
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/* Initialize TIM1 */
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pwm1 = (struct stm32_pwm_dev_s *) stm32_pwminitialize(1);
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if (pwm1 == NULL)
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{
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printf("ERROR: Failed to get PWM1 interface\n");
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ret = EXIT_FAILURE;
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goto errout;
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}
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highpri->pwm = pwm1;
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/* Setup PWM device */
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PWM_SETUP(pwm1);
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/* Set timer frequency */
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PWM_FREQ_UPDATE(pwm1, 1000);
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/* Set CCR1 */
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PWM_CCR_UPDATE(pwm1, 1, 0x0f00);
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/* Enable TIM1 OUT1 */
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PWM_OUTPUTS_ENABLE(pwm1, STM32_PWM_OUT1, true);
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#ifdef CONFIG_DEBUG_PWM_INFO
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/* Print debug */
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PWM_DUMP_REGS(pwm1);
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#endif
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#endif /* HIGHPRI_HAVE_TIM1 */
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#if !defined(CONFIG_STM32_ADC1_DMA) || defined(HIGHPRI_HAVE_INJECTED)
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/* Attach ADC12 ram vector if no DMA or injected channels support */
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ret = arm_ramvec_attach(STM32_IRQ_ADC12, adc12_handler);
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if (ret < 0)
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{
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fprintf(stderr, "highpri_main: ERROR: arm_ramvec_attach failed: %d\n",
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ret);
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ret = EXIT_FAILURE;
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goto errout;
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}
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/* Set the priority of the ADC12 interrupt vector */
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ret = up_prioritize_irq(STM32_IRQ_ADC12, NVIC_SYSH_HIGH_PRIORITY);
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if (ret < 0)
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{
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fprintf(stderr, "highpri_main: ERROR: up_prioritize_irq failed: %d\n",
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ret);
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ret = EXIT_FAILURE;
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goto errout;
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}
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up_enable_irq(STM32_IRQ_ADC12);
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#endif
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#ifdef CONFIG_STM32_ADC1_DMA
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/* Attach DMA1 CH1 ram vector if DMA */
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ret = arm_ramvec_attach(STM32_IRQ_DMA1CH1, dma1ch1_handler);
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if (ret < 0)
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{
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fprintf(stderr, "highpri_main: ERROR: arm_ramvec_attach failed: %d\n",
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ret);
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ret = EXIT_FAILURE;
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goto errout;
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}
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/* Set the priority of the DMA1CH1 interrupt vector */
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ret = up_prioritize_irq(STM32_IRQ_DMA1CH1, NVIC_SYSH_HIGH_PRIORITY);
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if (ret < 0)
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{
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fprintf(stderr, "highpri_main: ERROR: up_prioritize_irq failed: %d\n",
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ret);
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ret = EXIT_FAILURE;
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goto errout;
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}
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up_enable_irq(STM32_IRQ_DMA1CH1);
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#endif
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/* Setup ADC hardware */
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adc1->ad_ops->ao_setup(adc1);
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/* Configure regular channels trigger to T1CC1 */
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STM32_ADC_EXTCFG_SET(highpri->adc1,
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ADC1_EXTSEL_T1CC1 | ADC_EXTREG_EXTEN_DEFAULT);
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#ifndef CONFIG_STM32_ADC1_DMA
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/* Enable ADC regular conversion interrupts if no DMA */
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STM32_ADC_INT_ENABLE(highpri->adc1, ADC_IER_EOC);
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#else
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/* Register ADC buffer for DMA transfer */
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STM32_ADC_REGBUF_REGISTER(highpri->adc1, g_highpri.r_val, REG_NCHANNELS);
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#endif
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#ifdef HIGHPRI_HAVE_INJECTED
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/* Enable ADC injected sequence end interrupts */
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STM32_ADC_INT_ENABLE(highpri->adc1, ADC_IER_JEOS);
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#endif
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#ifdef HIGHPRI_HAVE_TIM1
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/* Enable timer counter after ADC configuration */
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PWM_TIM_ENABLE(pwm1, true);
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#endif
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while (1)
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{
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#ifndef CONFIG_STM32_ADC1_DMA
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/* Software trigger for regular sequence */
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adc1->ad_ops->ao_ioctl(adc1, IO_TRIGGER_REG, 0);
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nxsig_usleep(100);
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#endif
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#ifdef HIGHPRI_HAVE_INJECTED
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/* Software trigger for injected sequence */
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adc1->ad_ops->ao_ioctl(adc1, IO_TRIGGER_INJ, 0);
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nxsig_usleep(100);
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#endif
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/* Lock global data */
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g_highpri.lock = true;
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#ifndef CONFIG_STM32_ADC1_DMA
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printf("%" PRId32 " [%d] %0.3fV\n", g_highpri.cntr1, g_highpri.current,
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g_highpri.r_volt[g_highpri.current]);
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#else
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printf("%" PRId32 " ", g_highpri.cntr1);
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for (i = 0; i < REG_NCHANNELS; i += 1)
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{
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printf("r:[%d] %0.3fV, ", i, g_highpri.r_volt[i]);
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}
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printf("\n");
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#endif
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#ifdef HIGHPRI_HAVE_INJECTED
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/* Print data from injected channels */
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printf("%" PRId32 " ", g_highpri.cntr2);
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for (i = 0; i < INJ_NCHANNELS; i += 1)
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{
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printf("j:[%d] %0.3fV, ", i, g_highpri.j_volt[i]);
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}
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printf("\n");
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#endif
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/* Unlock global data */
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g_highpri.lock = false;
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nxsig_sleep(1);
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}
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errout:
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return ret;
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}
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#endif /* CONFIG_NUCLEOF302R8_HIGHPRI */
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