Jukka Laitinen 7b8eec3fa4 arch/risc-v/src/common/riscv_exception_common.S: Add support for > 2 CPUs ... Add a new configuration for CONFIG_N_IRQ_STACKS, whcih defaults to CONFIG_SMP_NCPUS or 1 - this allows configuring multiple IRQ stacks also in the case where SMP support is not needed - this is specifically needed in mpfs target, where "bootloader" build boots only on one hart, but the startup code executes on all harts and handles SW IRQs Also don't store/restore GP if RISCV_SAVE_GP is not defined. If the GP is not stored in fork, it can't be restored for new tasks Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>		2022-01-20 01:37:34 +08:00
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include	arch/risc-v/qemu-rv: Support both rv32/rv64 core	2022-01-15 11:42:01 +08:00
src	arch/risc-v/src/common/riscv_exception_common.S: Add support for > 2 CPUs	2022-01-20 01:37:34 +08:00
Kconfig	risc-v: Remove ARCH_RV_ISA_[F|D] use ARCH_HAVE_FPU instead	2022-01-15 11:42:01 +08:00