Jukka Laitinen 7b8eec3fa4 arch/risc-v/src/common/riscv_exception_common.S: Add support for > 2 CPUs ... Add a new configuration for CONFIG_N_IRQ_STACKS, whcih defaults to CONFIG_SMP_NCPUS or 1 - this allows configuring multiple IRQ stacks also in the case where SMP support is not needed - this is specifically needed in mpfs target, where "bootloader" build boots only on one hart, but the startup code executes on all harts and handles SW IRQs Also don't store/restore GP if RISCV_SAVE_GP is not defined. If the GP is not stored in fork, it can't be restored for new tasks Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>		2022-01-20 01:37:34 +08:00
..
bl602	net: use HTONS, NTOHS, HTONL, NTOHL macro in kernel code	2022-01-18 10:59:47 +01:00
c906	include: fix double include pre-processor guards	2022-01-16 11:11:14 -03:00
common	arch/risc-v/src/common/riscv_exception_common.S: Add support for > 2 CPUs	2022-01-20 01:37:34 +08:00
esp32c3	net: use HTONS, NTOHS, HTONL, NTOHL macro in kernel code	2022-01-18 10:59:47 +01:00
fe310	include: fix double include pre-processor guards	2022-01-16 11:11:14 -03:00
k210	arch/risc-v: Refine riscv_cpupause.c	2022-01-16 23:11:32 +08:00
litex	include: fix double include pre-processor guards	2022-01-16 11:11:14 -03:00
mpfs	arch/risc-v/src/common/riscv_exception_common.S: Add support for > 2 CPUs	2022-01-20 01:37:34 +08:00
opensbi	risc-v/opensbi: update to version 1.0	2022-01-04 15:50:25 +08:00
qemu-rv	risc-v: Remove ARCH_RV_ISA_[F|D] use ARCH_HAVE_FPU instead	2022-01-15 11:42:01 +08:00
rv32m1	include: fix double include pre-processor guards	2022-01-16 11:11:14 -03:00
.gitignore	build: Remve the unnecessary .gitignore	2020-05-23 18:00:40 +01:00
Makefile	make/allsyms: skip the unnecessary link operation	2021-12-28 23:47:10 -06:00