sergiotarxz/nuttx
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity
7c02432f0e
nuttx/arch/arm/src/armv7-r
History
chao.an 7c02432f0e arm/armv7-a/r: set the default CPU mode to System 
In SVC mode, the banked register will be inconsistent with the user mode register:

arch/arm/src/armv7-a/arm_vectors.S

 276   .globl  arm_syscall
 277   .globl  arm_vectorsvc
 278   .type arm_vectorsvc, %function
 279
 280 arm_vectorsvc:
...
 286   sub   sp, sp, #XCPTCONTEXT_SIZE        // < SVC mode SP
...
 308   stmia   r0, {r13, r14}^                // < USR mode SP/LR
...

[    2.200000] [ 4] [ ALERT] SYSCALL Entry: regs: 0x80202708 cmd: 4
[    2.200000] [ 4] [ ALERT]   R0: 00000004 80001229 00000001 80202018 00000000 00000000 00000000 802027d0
[    2.200000] [ 4] [ ALERT]   R8: 00000000 00000000 00000000 00000000 00000000 802027d0 1080f710 1080f710
[    2.200000] [ 4] [ ALERT] CPSR: 00000073
[    2.200000] [ 4] [ ALERT] SYSCALL Exit: regs: 0x80202708
[    2.200000] [ 4] [ ALERT]   R0: 1 80202018 1 80202018 0 0 0 802027d0
[    2.200000] [ 4] [ ALERT]   R8: 0 0 0 0 0 802027d0 1080f710 80001229
[    2.200000] [ 4] [ ALERT] CPSR: 00000070

SVC SP is 0x80202708
USR SP is 0x802027d0
0x802027d0 - 0x80202708 should be XCPTCONTEXT_SIZE

[    2.200000] [ 4] [ ALERT] SYSCALL Entry: regs: 0x80202708 cmd: 51
[    2.200000] [ 4] [ ALERT]   R0: 00000033 00000000 80202780 00000000 00000000 00000000 00000000 80202710
[    2.200000] [ 4] [ ALERT]   R8: 00000000 00000000 00000000 00000000 00000000 80202710 800039d5 800039b2
[    2.200000] [ 4] [ ALERT] CPSR: 00000070
[    2.200000] [ 4] [ ALERT] SYSCALL Exit: regs: 0x80202708
[    2.200000] [ 4] [ ALERT]   R0: 2b 0 80202780 0 0 0 0 80202710
[    2.200000] [ 4] [ ALERT]   R8: 0 0 0 0 0 10843d80 800039d5 10801425
[    2.200000] [ 4] [ ALERT] CPSR: 00000073

SVC SP is 0x80202708
USR SP is 0x80202710
SP overlap in SVC and USR mode

This commit change the default CPU mode to System and ensure the consistency of SP/LR in USR/SYS mode during syscall.

Signed-off-by: chao.an <anchao@xiaomi.com>
2022-03-14 19:54:53 +09:00
..
arm_cache.c armv7-a/r: use flush/clean_all if size large than cache size 2022-02-09 18:16:31 +01:00
arm_copyarmstate.c
arm_copyfullstate.c
arm_dataabort.c Don't include assert.h from public header file 2021-06-03 08:36:03 -07:00
arm_doirq.c arch: Merge up_arch.h into up_internal.h 2022-03-14 09:32:17 +02:00
arm_fetchadd.S arch/arm: Fix the style issue in assemble files 2021-04-04 14:39:16 +01:00
arm_fpuconfig.S Remove the double blank line from source files 2022-02-20 20:10:14 +01:00
arm_fullcontextrestore.S arch: Move the content from svcall.h to syscall.h 2022-02-27 22:54:13 +08:00
arm_gicv2.c arch: Merge up_arch.h into up_internal.h 2022-03-14 09:32:17 +02:00
arm_head.S arm/armv7-a/r: set the default CPU mode to System 2022-03-14 19:54:53 +09:00
arm_initialstate.c arm/armv7-a/r: set the default CPU mode to System 2022-03-14 19:54:53 +09:00
arm_l2cc_pl310.c arch: Merge up_arch.h into up_internal.h 2022-03-14 09:32:17 +02:00
arm_mpu.c armv7-m,armv7-r,armv8-m:MPU Add mpu_reset and ARM_MPU_EARLY_RESET 2021-10-23 03:58:26 -05:00
arm_prefetchabort.c Don't include assert.h from public header file 2021-06-03 08:36:03 -07:00
arm_restorefpu.S fix arm FPSCR typos in comments. 2022-02-17 01:08:11 +08:00
arm_savefpu.S fix arm FPSCR typos in comments. 2022-02-17 01:08:11 +08:00
arm_saveusercontext.S fix arm FPSCR typos in comments. 2022-02-17 01:08:11 +08:00
arm_schedulesigaction.c arm/armv7-a/r: set the default CPU mode to System 2022-03-14 19:54:53 +09:00
arm_sigdeliver.c arch: Merge up_arch.h into up_internal.h 2022-03-14 09:32:17 +02:00
arm_signal_dispatch.c arch: Move the content from svcall.h to syscall.h 2022-02-27 22:54:13 +08:00
arm_signal_handler.S arch: Move the content from svcall.h to syscall.h 2022-02-27 22:54:13 +08:00
arm_syscall.c arm/armv7-a/r: set the default CPU mode to System 2022-03-14 19:54:53 +09:00
arm_tcbinfo.c sched/tcbinfo: Fix the compile warning 2022-01-27 17:36:27 +08:00
arm_testset.S arch/*_testset: Fix few typos. 2021-08-25 00:20:20 +08:00
arm_undefinedinsn.c Fix error: implicit declaration of function 'up_cpu_index' 2022-01-20 23:21:21 +08:00
arm_vectoraddrexcptn.S arch/arm: Fix the style issue in assemble files 2021-04-04 14:39:16 +01:00
arm_vectors.S arm/armv7-a/r: set the default CPU mode to System 2022-03-14 19:54:53 +09:00
arm_vectortab.S arch/arm: Fix the style issue in assemble files 2021-04-04 14:39:16 +01:00
arm.h include: fix double include pre-processor guards 2022-01-16 11:11:14 -03:00
barriers.h include: fix double include pre-processor guards 2022-01-16 11:11:14 -03:00
cp15_cache_size.S armv7-a/r:cache: add cp15_cache_size function 2022-02-09 18:16:31 +01:00
cp15_cacheops.h armv7-a/r:cache: add cp15_cache_size function 2022-02-09 18:16:31 +01:00
cp15_clean_dcache_all.S armv7-a/armv7-r:cache: modify hardcode in cache set/way operation 2022-03-03 14:11:31 +08:00
cp15_clean_dcache.S arch: armv7-r: move references from License header 2021-04-07 06:43:20 -05:00
cp15_coherent_dcache.S arch: armv7-r: move references from License header 2021-04-07 06:43:20 -05:00
cp15_flush_dcache_all.S armv7-a/armv7-r:cache: modify hardcode in cache set/way operation 2022-03-03 14:11:31 +08:00
cp15_flush_dcache.S arch: armv7-r: move references from License header 2021-04-07 06:43:20 -05:00
cp15_invalidate_dcache_all.S armv7-a/armv7-r:cache: modify hardcode in cache set/way operation 2022-03-03 14:11:31 +08:00
cp15_invalidate_dcache.S arch: armv7-r: move references from License header 2021-04-07 06:43:20 -05:00
cp15.h arch: armv7-r: Gregory Nutt: update licenses to Apache 2021-04-07 06:43:20 -05:00
fpu.h
gic.h
Kconfig
l2cc_pl310.h
l2cc.h
mpcore.h
mpu.h arch: Merge up_arch.h into up_internal.h 2022-03-14 09:32:17 +02:00
sctlr.h
Toolchain.defs arch/Toolchain.defs: Replace --print-file-name=libgcc.a with --print-libgcc-file-name 2022-01-31 09:46:04 +01:00
vfork.S arch: Allocate the space from the beginning in up_stack_frame 2021-04-16 12:41:41 +09:00