580 lines
16 KiB
C
580 lines
16 KiB
C
/****************************************************************************
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* arch/arm/src/armv7-r/sctlr.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/* References:
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*
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* "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
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* Copyright 1996-1998, 2000, 2004-2012 ARM.
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* All rights reserved. ARM DDI 0406C.c (ID051414)
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*/
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#ifndef __ARCH_ARM_SRC_ARMV7_R_SCTLR_H
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#define __ARCH_ARM_SRC_ARMV7_R_SCTLR_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* CP15 c0 Registers ********************************************************/
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/* Main ID Register (MIDR): CRn=c0, opc1=0, CRm=c0, opc2=0
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* TODO: To be provided
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*/
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/* Cache Type Register (CTR): CRn=c0, opc1=0, CRm=c0, opc2=1
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* TODO: To be provided
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*/
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/* TCM Type Register (TCMTR): CRn=c0, opc1=0, CRm=c0, opc2=2
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* Details implementation defined.
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*/
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/* Aliases of Main ID register (MIDR): CRn=c0, opc1=0, CRm=c0, opc2=3,7
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* TODO: To be provided
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*/
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/* MPU Type Register (MPUIR): CRn=c0, opc1=0, CRm=c0, opc2=4
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* TODO: To be provided
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*/
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/* Multiprocessor Affinity Register (MPIDR): CRn=c0, opc1=0, CRm=c0, opc2=5
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* TODO: To be provided
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*/
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/* Revision ID Register (REVIDR): CRn=c0, opc1=0, CRm=c0, opc2=6
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* TODO: To be provided
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*/
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/* Processor Feature Register 0 (ID_PFR0): CRn=c0, opc1=0, CRm=c1, opc2=0
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* Processor Feature Register 1 (ID_PFR1): CRn=c0, opc1=0, CRm=c1, opc2=1
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* TODO: To be provided
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*/
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/* Debug Feature Register 0 (ID_DFR0): CRn=c0, opc1=0, CRm=c1, opc2=2
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* TODO: To be provided
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*/
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/* Auxiliary Feature Register 0 (ID_AFR0): CRn=c0, opc1=0, CRm=c1, opc2=3
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* TODO: To be provided
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*/
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/* Memory Model Features Register 0 (ID_MMFR0):
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* CRn=c0, opc1=0, CRm=c1, opc2=4
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* Memory Model Features Register 1 (ID_MMFR1):
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* CRn=c0, opc1=0, CRm=c1, opc2=5
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* Memory Model Features Register 2 (ID_MMFR2):
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* CRn=c0, opc1=0, CRm=c1, opc2=6
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* Memory Model Features Register 3 (ID_MMFR3):
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* CRn=c0, opc1=0, CRm=c1, opc2=7
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* TODO: To be provided
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*/
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/* Instruction Set Attributes Register 0 (ID_ISAR0):
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* CRn=c0, opc1=0, CRm=c2, opc2=0
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* Instruction Set Attributes Register 1 (ID_ISAR1):
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* CRn=c0, opc1=0, CRm=c2, opc2=1
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* Instruction Set Attributes Register 2 (ID_ISAR2):
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* CRn=c0, opc1=0, CRm=c2, opc2=2
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* Instruction Set Attributes Register 3 (ID_ISAR3):
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* CRn=c0, opc1=0, CRm=c2, opc2=3
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* Instruction Set Attributes Register 4 (ID_ISAR4):
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* CRn=c0, opc1=0, CRm=c2, opc2=4
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* Instruction Set Attributes Register 5 (ID_ISAR5):
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* CRn=c0, opc1=0, CRm=c2, opc2=5
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* Instruction Set Attributes Register 6-7 (ID_ISAR6-7).
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* Reserved.
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* TODO: Others to be provided
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*/
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/* Reserved: CRn=c0, opc1=0, CRm=c3-c7, opc2=* */
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/* Cache Size Identification Register (CCSIDR):
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* CRn=c0, opc1=1, CRm=c0, opc2=0
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* TODO: To be provided
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*/
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/* Cache Level ID Register (CLIDR): CRn=c0, opc1=1, CRm=c0, opc2=1
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* TODO: To be provided
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*/
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/* Auxiliary ID Register (AIDR): CRn=c0, opc1=1, CRm=c0, opc2=7
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* TODO: To be provided
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*/
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/* Cache Size Selection Register (CSSELR): CRn=c0, opc1=2, CRm=c0, opc2=0
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* TODO: To be provided
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*/
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/* CP15 c1 Registers ********************************************************/
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/* System Control Register (SCTLR): CRn=c1, opc1=0, CRm=c0, opc2=0
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*/
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#define SCTLR_M (1 << 0) /* Bit 0: MPU enable bit */
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#define SCTLR_A (1 << 1) /* Bit 1: Enables strict alignment of data */
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#define SCTLR_C (1 << 2) /* Bit 2: Determines if data can be cached */
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/* Bits 3-4: Reserved */
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#define SCTLR_CCP15BEN (1 << 5) /* Bit 5: CP15 barrier enable */
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/* Bit 6: Reserved */
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#define SCTLR_B (1 << 7) /* Bit 7: Should be zero on ARMv7-R */
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/* Bits 8-9: Reserved */
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#define SCTLR_SW (1 << 10) /* Bit 10: SWP/SWPB Enable bit */
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#define SCTLR_Z (1 << 11) /* Bit 11: Program flow prediction control */
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#define SCTLR_I (1 << 12) /* Bit 12: Determines if instructions can be cached */
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#define SCTLR_V (1 << 13) /* Bit 13: Vectors bit */
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#define SCTLR_RR (1 << 14) /* Bit 14: Cache replacement strategy */
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/* Bits 15-16: Reserved */
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#define SCTLR_BR (1 << 17) /* Bit 17: Background Region bit */
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/* Bit 18: Reserved */
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#define SCTLR_DZ (1 << 19) /* Bit 19: Divide by Zero fault enable bit */
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/* Bit 20: Reserved */
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#define SCTLR_FI (1 << 21) /* Bit 21: Fast interrupts configuration enable bit */
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#define SCTLR_U (1 << 22) /* Bit 22: Unaligned access model (always one) */
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#define SCTLR_VE (1 << 24) /* Bit 24: Interrupt Vectors Enable bit */
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#define SCTLR_EE (1 << 25) /* Bit 25: Determines the value the CPSR.E */
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#define SCTLR_NMFI (1 << 27) /* Bit 27: Non-maskable FIQ (NMFI) support */
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/* Bits 28-29: Reserved */
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#define SCTLR_TE (1 << 30) /* Bit 30: Thumb exception enable */
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#define SCTLR_IE (1 << 31) /* Bit 31: Instruction endian-ness */
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/* Auxiliary Control Register (ACTLR): CRn=c1, opc1=0, CRm=c0, opc2=1
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* Implementation defined
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*/
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/* Coprocessor Access Control Register (CPACR):
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* CRn=c1, opc1=0, CRm=c0, opc2=2
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* TODO: To be provided
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*/
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/* CP15 c2-c4 Registers *****************************************************/
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/* Not used on ARMv7-R */
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/* CP15 c5 Registers ********************************************************/
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/* Data Fault Status Register (DFSR): CRn=c5, opc1=0, CRm=c0, opc2=0
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* TODO: To be provided
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*/
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/* Instruction Fault Status Register (IFSR): CRn=c5, opc1=0, CRm=c0, opc2=1
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* TODO: To be provided
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*/
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/* Auxiliary DFSR (ADFSR): CRn=c5, opc1=0, CRm=c1, opc2=0
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* TODO: To be provided
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*/
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/* Auxiliary IFSR (AIFSR): CRn=c5, opc1=0, CRm=c1, opc2=1
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* TODO: To be provided
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*/
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/* CP15 c6 Registers ********************************************************/
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/* Data Fault Address Register(DFAR): CRn=c6, opc1=0, CRm=c0, opc2=0
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*
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* Holds the MVA of the faulting address when a synchronous fault occurs
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*/
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/* Instruction Fault Address Register(IFAR): CRn=c6, opc1=0, CRm=c0, opc2=1
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*
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* Holds the MVA of the faulting address of the instruction that caused a
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* prefetch abort.
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*/
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/* Data Region Base Address Register (DRBAR): CRn=c6, opc1=0, CRm=c1, opc2=0
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* TODO: To be provided
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*/
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/* Instruction Region Base Address Register (IRBAR):
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* CRn=c6, opc1=0, CRm=c1, opc2=1
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* TODO: To be provided
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*/
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/* Data Region Size and Enable Register (DRSR):
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* CRn=c6, opc1=0, CRm=c1, opc2=2
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* TODO: To be provided
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*/
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/* Instruction Region Size and Enable Register (IRSR):
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* CRn=c6, opc1=0, CRm=c1, opc2=3
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* TODO: To be provided
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*/
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/* Data Region Access Control Register (DRACR):
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* CRn=c6, opc1=0, CRm=c1, opc2=4
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* TODO: To be provided
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*/
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/* Instruction Region Access Control Register (IRACR):
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* CRn=c6, opc1=0, CRm=c1, opc2=5
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* TODO: To be provided
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*/
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/* MPU Region Number Register (RGNR):
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* CRn=c6, opc1=0, CRm=c2, opc2=0
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* TODO: To be provided
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*/
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/* CP15 c7 Registers ********************************************************/
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/* See cp15_cacheops.h */
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/* CP15 c8 Registers ********************************************************/
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/* Not used on ARMv7-R */
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/* CP15 c9 Registers ********************************************************/
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/* 32-bit Performance Monitors Control Register (PMCR):
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* CRn=c9, opc1=0, CRm=c12, opc2=0
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* TODO: To be provided
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*/
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#define PCMR_E (1 << 0) /* Enable all counters */
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#define PCMR_P (1 << 1) /* Reset all counter eventts (except PMCCNTR) */
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#define PCMR_C (1 << 2) /* Reset cycle counter (PMCCNTR) to zero */
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#define PCMR_D (1 << 3) /* Enable cycle counter clock (PMCCNTR) divider */
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#define PCMR_X (1 << 4) /* Export of events is enabled */
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#define PCMR_DP (1 << 5) /* Disable PMCCNTR if event counting is prohibited */
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#define PCMR_N_SHIFT (11) /* Bits 11-15: Number of event counters */
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#define PCMR_N_MASK (0x1f << PCMR_N_SHIFT)
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#define PCMR_IDCODE_SHIFT (16) /* Bits 16-23: Identification code */
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#define PCMR_IDCODE_MASK (0xff << PCMR_IDCODE_SHIFT)
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#define PCMR_IMP_SHIFT (24) /* Bits 24-31: Implementer code */
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#define PCMR_IMP_MASK (0xff << PCMR_IMP_SHIFT)
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/* 32-bit Performance Monitors Count Enable Set register (PMCNTENSET):
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* CRn=c9, opc1=0, CRm=c12, opc2=1
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* TODO: To be provided
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*/
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/* 32-bit Performance Monitors Count Enable Clear register (PMCNTENCLR):
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* CRn=c9, opc1=0, CRm=c12, opc2=2
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* TODO: To be provided
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*/
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/* 32-bit Performance Monitors Overflow Flag Status Register (PMOVSR):
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* CRn=c9, opc1=0, CRm=c12, opc2=3
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* TODO: To be provided
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*/
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/* 32-bit Performance Monitors Software Increment register (PMSWINC):
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* CRn=c9, opc1=0, CRm=c12, opc2=4
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* TODO: To be provided
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*/
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/* 32-bit Performance Monitors Event Counter Selection Register (PMSELR):
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* CRn=c9, opc1=0, CRm=c12, opc2=5
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* TODO: To be provided
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*/
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/* 32-bit Performance Monitors Common Event Identification (PMCEID0):
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* CRn=c9, opc1=0, CRm=c12, opc2=6
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* TODO: To be provided
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*/
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/* 32-bit Performance Monitors Common Event Identification (PMCEID1):
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* CRn=c9, opc1=0, CRm=c12, opc2=7
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* TODO: To be provided
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*/
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/* 32-bit Performance Monitors Cycle Count Register (PMCCNTR):
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* CRn=c9, opc1=0, CRm=c13, opc2=0
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* TODO: To be provided
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*/
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/* 32-bit Performance Monitors Event Type Select Register (PMXEVTYPER):
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* CRn=c9, opc1=0, CRm=c13, opc2=1
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* TODO: To be provided
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*/
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/* 32-bit Performance Monitors Event Count Register (PMXEVCNTR):
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* CRn=c9, opc1=0, CRm=c13, opc2=2
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* TODO: To be provided
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*/
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/* 32-bit Performance Monitors User Enable Register (PMUSERENR):
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* CRn=c9, opc1=0, CRm=c14, opc2=0
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* TODO: To be provided
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*/
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/* 32-bit Performance Monitors Interrupt Enable Set register (PMINTENSET):
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* CRn=c9, opc1=0, CRm=c14, opc2=1
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* TODO: To be provided
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*/
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/* 32-bit Performance Monitors Interrupt Enable Clear register (PMINTENCLR):
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* CRn=c9, opc1=0, CRm=c14, opc2=2
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* TODO: To be provided
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*/
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/* CP15 c10 Registers *******************************************************/
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/* Not used on ARMv7-R */
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/* CP15 c11 Registers *******************************************************/
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/* Reserved for implementation defined DMA functions */
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/* CP15 c12 Registers *******************************************************/
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/* Not used on ARMv7-R */
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/* CP15 c13 Registers *******************************************************/
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/* Context ID Register (CONTEXTIDR): CRn=c13, opc1=0, CRm=c0, opc2=1
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* 32-Bit ContextID value.
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*/
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/* User Read/Write (TPIDRURW): CRn=c13, opc1=0, CRm=c0, opc2=2
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* TODO: To be provided
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*/
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/* User Read Only (TPIDRURO): CRn=c13, opc1=0, CRm=c0, opc2=3
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* TODO: To be provided
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*/
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/* PL1 only (TPIDRPRW): CRn=c13, opc1=0, CRm=c0, opc2=4
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* TODO: To be provided
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*/
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/* CP15 c14 Registers *******************************************************/
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/* Counter Frequency register (CNTFRQ): CRn=c14, opc1=0, CRm=c0, opc2=0
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* TODO: To be provided
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*/
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/* Timer PL1 Control register (CNTKCTL): CRn=c14, opc1=0, CRm=c1, opc2=0
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* TODO: To be provided
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*/
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/* PL1 Physical TimerValue register (CNTP_TVAL):
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* CRn=c14, opc1=0, CRm=c2, opc2=0
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* TODO: To be provided
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*/
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/* PL1 Physical Timer Control register (CNTP_CTL):
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* CRn=c14, opc1=0, CRm=c2, opc2=0
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* TODO: To be provided
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*/
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/* Virtual TimerValue register (CNTV_TVAL): CRn=c14, opc1=0, CRm=c3, opc2=0
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* TODO: To be provided
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*/
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/* Virtual Timer Control register (CNTV_CTL): CRn=c14, opc1=0, CRm=c3, opc2=0
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* TODO: To be provided
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*/
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/* 64-bit Physical Count register (CNTPCT): CRn=c14, opc1=0, CRm=c14, opc2=n
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* TODO: To be provided
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*/
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/* Virtual Count register (CNTVCT): CRn=c14, opc1=1, CRm=c14, opc2=n
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* TODO: To be provided
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*/
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/* PL1 Physical Timer CompareValue register (CNTP_CVAL):
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* CRn=c14, opc1=2, CRm=c14, opc2=n
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* TODO: To be provided
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*/
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/* Virtual Timer CompareValue register (CNTV_CVAL):
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* CRn=c14, opc1=3, CRm=c14, opc2=n
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* TODO: To be provided
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*/
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/* CP15 c15 Registers *******************************************************/
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/* Implementation defined */
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/****************************************************************************
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* Assembly Macros
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****************************************************************************/
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#ifdef __ASSEMBLY__
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/* Get the device ID */
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.macro cp15_rdid, id
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mrc p15, 0, \id, c0, c0, 0
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.endm
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/* Read/write the system control register (SCTLR) */
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.macro cp15_rdsctlr, sctlr
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mrc p15, 0, \sctlr, c1, c0, 0
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.endm
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.macro cp15_wrsctlr, sctlr
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mcr p15, 0, \sctlr, c1, c0, 0
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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.endm
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#endif /* __ASSEMBLY__ */
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/****************************************************************************
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* Inline Functions
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****************************************************************************/
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#ifndef __ASSEMBLY__
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/* Get the device ID */
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static inline unsigned int cp15_rdid(void)
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{
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unsigned int id;
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__asm__ __volatile__
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(
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"\tmrc p15, 0, %0, c0, c0, 0"
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: "=r" (id)
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:
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: "memory"
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);
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return id;
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}
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/* Read/write the system control register (SCTLR) */
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static inline unsigned int cp15_rdsctlr(void)
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{
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unsigned int sctlr;
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__asm__ __volatile__
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(
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"\tmrc p15, 0, %0, c1, c0, 0\n"
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: "=r" (sctlr)
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:
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: "memory"
|
|
);
|
|
|
|
return sctlr;
|
|
}
|
|
|
|
static inline void cp15_wrsctlr(unsigned int sctlr)
|
|
{
|
|
__asm__ __volatile__
|
|
(
|
|
"\tmcr p15, 0, %0, c1, c0, 0\n"
|
|
"\tnop\n"
|
|
"\tnop\n"
|
|
"\tnop\n"
|
|
"\tnop\n"
|
|
"\tnop\n"
|
|
"\tnop\n"
|
|
"\tnop\n"
|
|
"\tnop\n"
|
|
:
|
|
: "r" (sctlr)
|
|
: "memory"
|
|
);
|
|
}
|
|
|
|
/* Read/write the implementation defined Auxiliary Control Register (ACTLR) */
|
|
|
|
static inline unsigned int cp15_rdactlr(void)
|
|
{
|
|
unsigned int actlr;
|
|
__asm__ __volatile__
|
|
(
|
|
"\tmrc p15, 0, %0, c1, c0, 1\n"
|
|
: "=r" (actlr)
|
|
:
|
|
: "memory"
|
|
);
|
|
|
|
return actlr;
|
|
}
|
|
|
|
static inline void cp15_wractlr(unsigned int actlr)
|
|
{
|
|
__asm__ __volatile__
|
|
(
|
|
"\tmcr p15, 0, %0, c1, c0, 1\n"
|
|
:
|
|
: "r" (actlr)
|
|
: "memory"
|
|
);
|
|
}
|
|
|
|
/* Read/write the Performance Monitor Control Register (PMCR) */
|
|
|
|
static inline unsigned int cp15_rdpmcr(void)
|
|
{
|
|
unsigned int pmcr;
|
|
__asm__ __volatile__
|
|
(
|
|
"\tmrc p15, 0, %0, c9, c12, 0\n"
|
|
: "=r" (pmcr)
|
|
:
|
|
: "memory"
|
|
);
|
|
|
|
return pmcr;
|
|
}
|
|
|
|
static inline void cp15_wrpmcr(unsigned int pmcr)
|
|
{
|
|
__asm__ __volatile__
|
|
(
|
|
"\tmcr p15, 0, %0, c9, c12, 0\n"
|
|
:
|
|
: "r" (pmcr)
|
|
: "memory"
|
|
);
|
|
}
|
|
|
|
#endif /* __ASSEMBLY__ */
|
|
|
|
/****************************************************************************
|
|
* Public Data
|
|
****************************************************************************/
|
|
|
|
/****************************************************************************
|
|
* Public Function Prototypes
|
|
****************************************************************************/
|
|
|
|
#ifndef __ASSEMBLY__
|
|
#ifdef __cplusplus
|
|
#define EXTERN extern "C"
|
|
extern "C"
|
|
{
|
|
#else
|
|
#define EXTERN extern
|
|
#endif
|
|
|
|
#undef EXTERN
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
#endif /* __ASSEMBLY__ */
|
|
|
|
#endif /* __ARCH_ARM_SRC_ARMV7_R_SCTLR_H */
|