fc46135ebc
Improvements in STM32 ADC, minor changes in STM32 PWM, DMA, HRTIM and add some highpri ADC examples arch/arch/src/stm32/stm32_adc: fix RCC reset logic arch/arch/src/stm32/stm32_adc: move sample time change functions to low-level ADC ops arch/arch/src/stm32/stm32_adc: configurable ADC DMA mode (one shot mode, circular mode) arch/arch/src/stm32/stm32_pwm: remove llops_get interface. We can use structure casting to get pwm low-level ops arch/arch/src/stm32/stm32_pwm: add timer enable/disable and frequency update to low-level ops arch/src/arm/stm32: remove redundant stm32f33xxx_dma.c arch/arm/src/stm32/stm32f40xxx_dma.c: add interfaces to interact with highp priority DMA interupts arch/src/arm/stm32/stm32_hrtim: do not enable timers on startup if option from Kconfig selected and add interface to enable/disable timers arch/src/arm/stm32/stm32_hrtim: fix some warnings configs/nucleo-f334r8/highpri: update configuration due to changes in stm32_adc configs/stm32f334-disco/buckboost: update configuration due to changes in stm32_adc configs/nucleo-f334r8/highpri: add support for ADC injected sequence, add triggering from TIM1 configs/nucleo-f302r8/highpri: add high priority ADC interrupts example configs/stm32f429i-disco/highpri: add high priority ADC interrupts example Approved-by: GregoryN <gnutt@nuttx.org>
1086 lines
32 KiB
C
1086 lines
32 KiB
C
/************************************************************************************
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* arch/arm/src/stm32/stm32_pwm.h
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*
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* Copyright (C) 2011, 2015 Gregory Nutt. All rights reserved.
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* Copyright (C) 2015 Omni Hoverboards Inc. All rights reserved.
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* Authors: Gregory Nutt <gnutt@nuttx.org>
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* Paul Alexander Patience <paul-a.patience@polymtl.ca>
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* Mateusz Szafoni <raiden00@railab.me>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32_STM32_PWM_H
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#define __ARCH_ARM_SRC_STM32_STM32_PWM_H
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/* The STM32 does not have dedicated PWM hardware. Rather, pulsed output control
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* is a capabilitiy of the STM32 timers. The logic in this file implements the
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* lower half of the standard, NuttX PWM interface using the STM32 timers. That
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* interface is described in include/nuttx/drivers/pwm.h.
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*/
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Configuration ********************************************************************/
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/* Timer devices may be used for different purposes. One special purpose is
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* to generate modulated outputs for such things as motor control. If CONFIG_STM32_TIMn
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* is defined then the CONFIG_STM32_TIMn_PWM must also be defined to indicate that
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* timer "n" is intended to be used for pulsed output signal generation.
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*/
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#ifndef CONFIG_STM32_TIM1
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# undef CONFIG_STM32_TIM1_PWM
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#endif
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#ifndef CONFIG_STM32_TIM2
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# undef CONFIG_STM32_TIM2_PWM
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#endif
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#ifndef CONFIG_STM32_TIM3
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# undef CONFIG_STM32_TIM3_PWM
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#endif
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#ifndef CONFIG_STM32_TIM4
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# undef CONFIG_STM32_TIM4_PWM
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#endif
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#ifndef CONFIG_STM32_TIM5
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# undef CONFIG_STM32_TIM5_PWM
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#endif
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#ifndef CONFIG_STM32_TIM8
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# undef CONFIG_STM32_TIM8_PWM
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#endif
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#ifndef CONFIG_STM32_TIM9
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# undef CONFIG_STM32_TIM9_PWM
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#endif
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#ifndef CONFIG_STM32_TIM10
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# undef CONFIG_STM32_TIM10_PWM
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#endif
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#ifndef CONFIG_STM32_TIM11
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# undef CONFIG_STM32_TIM11_PWM
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#endif
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#ifndef CONFIG_STM32_TIM12
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# undef CONFIG_STM32_TIM12_PWM
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#endif
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#ifndef CONFIG_STM32_TIM13
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# undef CONFIG_STM32_TIM13_PWM
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#endif
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#ifndef CONFIG_STM32_TIM14
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# undef CONFIG_STM32_TIM14_PWM
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#endif
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#ifndef CONFIG_STM32_TIM15
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# undef CONFIG_STM32_TIM15_PWM
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#endif
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#ifndef CONFIG_STM32_TIM16
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# undef CONFIG_STM32_TIM16_PWM
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#endif
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#ifndef CONFIG_STM32_TIM17
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# undef CONFIG_STM32_TIM17_PWM
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#endif
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/* The basic timers (timer 6 and 7) are not capable of generating output pulses */
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#undef CONFIG_STM32_TIM6_PWM
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#undef CONFIG_STM32_TIM7_PWM
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/* Check if PWM support for any channel is enabled. */
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#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM2_PWM) || \
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defined(CONFIG_STM32_TIM3_PWM) || defined(CONFIG_STM32_TIM4_PWM) || \
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defined(CONFIG_STM32_TIM5_PWM) || defined(CONFIG_STM32_TIM8_PWM) || \
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defined(CONFIG_STM32_TIM9_PWM) || defined(CONFIG_STM32_TIM10_PWM) || \
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defined(CONFIG_STM32_TIM11_PWM) || defined(CONFIG_STM32_TIM12_PWM) || \
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defined(CONFIG_STM32_TIM13_PWM) || defined(CONFIG_STM32_TIM14_PWM) || \
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defined(CONFIG_STM32_TIM15_PWM) || defined(CONFIG_STM32_TIM16_PWM) || \
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defined(CONFIG_STM32_TIM17_PWM)
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#include <arch/board/board.h>
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#include "chip/stm32_tim.h"
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#ifdef CONFIG_STM32_PWM_MULTICHAN
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# ifndef CONFIG_PWM_MULTICHAN
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# error CONFIG_STM32_PWM_MULTICHAN enabled but CONFIG_PWM_MULTICHAN not set!
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# endif
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#endif
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#ifdef CONFIG_PWM_MULTICHAN
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#ifdef CONFIG_STM32_TIM1_CHANNEL1
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# define PWM_TIM1_CHANNEL1 1
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#else
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# define PWM_TIM1_CHANNEL1 0
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#endif
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#ifdef CONFIG_STM32_TIM1_CHANNEL2
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# define PWM_TIM1_CHANNEL2 1
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#else
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# define PWM_TIM1_CHANNEL2 0
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#endif
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#ifdef CONFIG_STM32_TIM1_CHANNEL3
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# define PWM_TIM1_CHANNEL3 1
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#else
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# define PWM_TIM1_CHANNEL3 0
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#endif
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#ifdef CONFIG_STM32_TIM1_CHANNEL4
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# define PWM_TIM1_CHANNEL4 1
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#else
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# define PWM_TIM1_CHANNEL4 0
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#endif
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#define PWM_TIM1_NCHANNELS (PWM_TIM1_CHANNEL1 + PWM_TIM1_CHANNEL2 + \
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PWM_TIM1_CHANNEL3 + PWM_TIM1_CHANNEL4)
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#ifdef CONFIG_STM32_TIM2_CHANNEL1
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# define PWM_TIM2_CHANNEL1 1
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#else
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# define PWM_TIM2_CHANNEL1 0
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#endif
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#ifdef CONFIG_STM32_TIM2_CHANNEL2
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# define PWM_TIM2_CHANNEL2 1
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#else
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# define PWM_TIM2_CHANNEL2 0
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#endif
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#ifdef CONFIG_STM32_TIM2_CHANNEL3
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# define PWM_TIM2_CHANNEL3 1
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#else
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# define PWM_TIM2_CHANNEL3 0
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#endif
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#ifdef CONFIG_STM32_TIM2_CHANNEL4
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# define PWM_TIM2_CHANNEL4 1
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#else
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# define PWM_TIM2_CHANNEL4 0
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#endif
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#define PWM_TIM2_NCHANNELS (PWM_TIM2_CHANNEL1 + PWM_TIM2_CHANNEL2 + \
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PWM_TIM2_CHANNEL3 + PWM_TIM2_CHANNEL4)
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#ifdef CONFIG_STM32_TIM3_CHANNEL1
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# define PWM_TIM3_CHANNEL1 1
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#else
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# define PWM_TIM3_CHANNEL1 0
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#endif
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#ifdef CONFIG_STM32_TIM3_CHANNEL2
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# define PWM_TIM3_CHANNEL2 1
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#else
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# define PWM_TIM3_CHANNEL2 0
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#endif
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#ifdef CONFIG_STM32_TIM3_CHANNEL3
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# define PWM_TIM3_CHANNEL3 1
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#else
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# define PWM_TIM3_CHANNEL3 0
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#endif
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#ifdef CONFIG_STM32_TIM3_CHANNEL4
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# define PWM_TIM3_CHANNEL4 1
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#else
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# define PWM_TIM3_CHANNEL4 0
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#endif
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#define PWM_TIM3_NCHANNELS (PWM_TIM3_CHANNEL1 + PWM_TIM3_CHANNEL2 + \
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PWM_TIM3_CHANNEL3 + PWM_TIM3_CHANNEL4)
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#ifdef CONFIG_STM32_TIM4_CHANNEL1
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# define PWM_TIM4_CHANNEL1 1
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#else
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# define PWM_TIM4_CHANNEL1 0
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#endif
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#ifdef CONFIG_STM32_TIM4_CHANNEL2
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# define PWM_TIM4_CHANNEL2 1
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#else
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# define PWM_TIM4_CHANNEL2 0
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#endif
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#ifdef CONFIG_STM32_TIM4_CHANNEL3
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# define PWM_TIM4_CHANNEL3 1
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#else
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# define PWM_TIM4_CHANNEL3 0
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#endif
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#ifdef CONFIG_STM32_TIM4_CHANNEL4
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# define PWM_TIM4_CHANNEL4 1
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#else
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# define PWM_TIM4_CHANNEL4 0
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#endif
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#define PWM_TIM4_NCHANNELS (PWM_TIM4_CHANNEL1 + PWM_TIM4_CHANNEL2 + \
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PWM_TIM4_CHANNEL3 + PWM_TIM4_CHANNEL4)
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#ifdef CONFIG_STM32_TIM5_CHANNEL1
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# define PWM_TIM5_CHANNEL1 1
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#else
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# define PWM_TIM5_CHANNEL1 0
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#endif
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#ifdef CONFIG_STM32_TIM5_CHANNEL2
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# define PWM_TIM5_CHANNEL2 1
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#else
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# define PWM_TIM5_CHANNEL2 0
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#endif
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#ifdef CONFIG_STM32_TIM5_CHANNEL3
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# define PWM_TIM5_CHANNEL3 1
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#else
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# define PWM_TIM5_CHANNEL3 0
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#endif
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#ifdef CONFIG_STM32_TIM5_CHANNEL4
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# define PWM_TIM5_CHANNEL4 1
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#else
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# define PWM_TIM5_CHANNEL4 0
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#endif
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#define PWM_TIM5_NCHANNELS (PWM_TIM5_CHANNEL1 + PWM_TIM5_CHANNEL2 + \
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PWM_TIM5_CHANNEL3 + PWM_TIM5_CHANNEL4)
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#ifdef CONFIG_STM32_TIM8_CHANNEL1
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# define PWM_TIM8_CHANNEL1 1
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#else
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# define PWM_TIM8_CHANNEL1 0
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#endif
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#ifdef CONFIG_STM32_TIM8_CHANNEL2
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# define PWM_TIM8_CHANNEL2 1
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#else
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# define PWM_TIM8_CHANNEL2 0
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#endif
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#ifdef CONFIG_STM32_TIM8_CHANNEL3
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# define PWM_TIM8_CHANNEL3 1
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#else
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# define PWM_TIM8_CHANNEL3 0
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#endif
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#ifdef CONFIG_STM32_TIM8_CHANNEL4
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# define PWM_TIM8_CHANNEL4 1
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#else
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# define PWM_TIM8_CHANNEL4 0
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#endif
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#define PWM_TIM8_NCHANNELS (PWM_TIM8_CHANNEL1 + PWM_TIM8_CHANNEL2 + \
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PWM_TIM8_CHANNEL3 + PWM_TIM8_CHANNEL4)
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#ifdef CONFIG_STM32_TIM9_CHANNEL1
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# define PWM_TIM9_CHANNEL1 1
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#else
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# define PWM_TIM9_CHANNEL1 0
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#endif
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#ifdef CONFIG_STM32_TIM9_CHANNEL2
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# define PWM_TIM9_CHANNEL2 1
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#else
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# define PWM_TIM9_CHANNEL2 0
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#endif
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#define PWM_TIM9_NCHANNELS (PWM_TIM9_CHANNEL1 + PWM_TIM9_CHANNEL2)
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#ifdef CONFIG_STM32_TIM10_CHANNEL1
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# define PWM_TIM10_CHANNEL1 1
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#else
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# define PWM_TIM10_CHANNEL1 0
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#endif
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#define PWM_TIM10_NCHANNELS (PWM_TIM10_CHANNEL1)
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#ifdef CONFIG_STM32_TIM11_CHANNEL1
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# define PWM_TIM11_CHANNEL1 1
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#else
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# define PWM_TIM11_CHANNEL1 0
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#endif
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#define PWM_TIM11_NCHANNELS (PWM_TIM11_CHANNEL1)
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#ifdef CONFIG_STM32_TIM12_CHANNEL1
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# define PWM_TIM12_CHANNEL1 1
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#else
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# define PWM_TIM12_CHANNEL1 0
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#endif
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#ifdef CONFIG_STM32_TIM12_CHANNEL2
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# define PWM_TIM12_CHANNEL2 1
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#else
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# define PWM_TIM12_CHANNEL2 0
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#endif
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#define PWM_TIM12_NCHANNELS (PWM_TIM12_CHANNEL1 + PWM_TIM12_CHANNEL2)
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#ifdef CONFIG_STM32_TIM13_CHANNEL1
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# define PWM_TIM13_CHANNEL1 1
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#else
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# define PWM_TIM13_CHANNEL1 0
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#endif
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#define PWM_TIM13_NCHANNELS (PWM_TIM13_CHANNEL1)
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#ifdef CONFIG_STM32_TIM14_CHANNEL1
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# define PWM_TIM14_CHANNEL1 1
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#else
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# define PWM_TIM14_CHANNEL1 0
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#endif
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#define PWM_TIM14_NCHANNELS (PWM_TIM14_CHANNEL1)
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#ifdef CONFIG_STM32_TIM15_CHANNEL1
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# define PWM_TIM15_CHANNEL1 1
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#else
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# define PWM_TIM15_CHANNEL1 0
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#endif
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#ifdef CONFIG_STM32_TIM15_CHANNEL2
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# define PWM_TIM15_CHANNEL2 1
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#else
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# define PWM_TIM15_CHANNEL2 0
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#endif
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#define PWM_TIM15_NCHANNELS (PWM_TIM15_CHANNEL1 + PWM_TIM15_CHANNEL2)
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#ifdef CONFIG_STM32_TIM16_CHANNEL1
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# define PWM_TIM16_CHANNEL1 1
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#else
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# define PWM_TIM16_CHANNEL1 0
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#endif
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#define PWM_TIM16_NCHANNELS PWM_TIM16_CHANNEL1
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#ifdef CONFIG_STM32_TIM17_CHANNEL1
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# define PWM_TIM17_CHANNEL1 1
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#else
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# define PWM_TIM17_CHANNEL1 0
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#endif
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#define PWM_TIM17_NCHANNELS PWM_TIM17_CHANNEL1
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#else /* !CONFIG_PWM_MULTICHAN */
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/* For each timer that is enabled for PWM usage, we need the following additional
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* configuration settings:
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*
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* CONFIG_STM32_TIMx_CHANNEL - Specifies the timer output channel {1,..,4}
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* PWM_TIMx_CHn - One of the values defined in chip/stm32*_pinmap.h. In the case
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* where there are multiple pin selections, the correct setting must be provided
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* in the arch/board/board.h file.
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*
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* NOTE: The STM32 timers are each capable of generating different signals on
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* each of the four channels with different duty cycles. That capability is
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* not supported by this driver: Only one output channel per timer.
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*/
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#ifdef CONFIG_STM32_TIM1_PWM
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# if !defined(CONFIG_STM32_TIM1_CHANNEL)
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# error "CONFIG_STM32_TIM1_CHANNEL must be provided"
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# elif CONFIG_STM32_TIM1_CHANNEL == 1
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# define CONFIG_STM32_TIM1_CHANNEL1 1
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# define CONFIG_STM32_TIM1_CH1MODE CONFIG_STM32_TIM1_CHMODE
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# elif CONFIG_STM32_TIM1_CHANNEL == 2
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# define CONFIG_STM32_TIM1_CHANNEL2 1
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# define CONFIG_STM32_TIM1_CH2MODE CONFIG_STM32_TIM1_CHMODE
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# elif CONFIG_STM32_TIM1_CHANNEL == 3
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# define CONFIG_STM32_TIM1_CHANNEL3 1
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# define CONFIG_STM32_TIM1_CH3MODE CONFIG_STM32_TIM1_CHMODE
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# elif CONFIG_STM32_TIM1_CHANNEL == 4
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# define CONFIG_STM32_TIM1_CHANNEL4 1
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# define CONFIG_STM32_TIM1_CH4MODE CONFIG_STM32_TIM1_CHMODE
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# else
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# error "Unsupported value of CONFIG_STM32_TIM1_CHANNEL"
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# endif
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# define PWM_TIM1_NCHANNELS 1
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#endif
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#ifdef CONFIG_STM32_TIM2_PWM
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# if !defined(CONFIG_STM32_TIM2_CHANNEL)
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# error "CONFIG_STM32_TIM2_CHANNEL must be provided"
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# elif CONFIG_STM32_TIM2_CHANNEL == 1
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# define CONFIG_STM32_TIM2_CHANNEL1 1
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# define CONFIG_STM32_TIM2_CH1MODE CONFIG_STM32_TIM2_CHMODE
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# elif CONFIG_STM32_TIM2_CHANNEL == 2
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# define CONFIG_STM32_TIM2_CHANNEL2 1
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# define CONFIG_STM32_TIM2_CH2MODE CONFIG_STM32_TIM2_CHMODE
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# elif CONFIG_STM32_TIM2_CHANNEL == 3
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# define CONFIG_STM32_TIM2_CHANNEL3 1
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# define CONFIG_STM32_TIM2_CH3MODE CONFIG_STM32_TIM2_CHMODE
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# elif CONFIG_STM32_TIM2_CHANNEL == 4
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# define CONFIG_STM32_TIM2_CHANNEL4 1
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# define CONFIG_STM32_TIM2_CH4MODE CONFIG_STM32_TIM2_CHMODE
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# else
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# error "Unsupported value of CONFIG_STM32_TIM2_CHANNEL"
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# endif
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# define PWM_TIM2_NCHANNELS 1
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#endif
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#ifdef CONFIG_STM32_TIM3_PWM
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# if !defined(CONFIG_STM32_TIM3_CHANNEL)
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# error "CONFIG_STM32_TIM3_CHANNEL must be provided"
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# elif CONFIG_STM32_TIM3_CHANNEL == 1
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# define CONFIG_STM32_TIM3_CHANNEL1 1
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# define CONFIG_STM32_TIM3_CH1MODE CONFIG_STM32_TIM3_CHMODE
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# elif CONFIG_STM32_TIM3_CHANNEL == 2
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# define CONFIG_STM32_TIM3_CHANNEL2 1
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# define CONFIG_STM32_TIM3_CH2MODE CONFIG_STM32_TIM3_CHMODE
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# elif CONFIG_STM32_TIM3_CHANNEL == 3
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# define CONFIG_STM32_TIM3_CHANNEL3 1
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# define CONFIG_STM32_TIM3_CH3MODE CONFIG_STM32_TIM3_CHMODE
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# elif CONFIG_STM32_TIM3_CHANNEL == 4
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# define CONFIG_STM32_TIM3_CHANNEL4 1
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# define CONFIG_STM32_TIM3_CH4MODE CONFIG_STM32_TIM3_CHMODE
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# else
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# error "Unsupported value of CONFIG_STM32_TIM3_CHANNEL"
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# endif
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# define PWM_TIM3_NCHANNELS 1
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#endif
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#ifdef CONFIG_STM32_TIM4_PWM
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# if !defined(CONFIG_STM32_TIM4_CHANNEL)
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# error "CONFIG_STM32_TIM4_CHANNEL must be provided"
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# elif CONFIG_STM32_TIM4_CHANNEL == 1
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# define CONFIG_STM32_TIM4_CHANNEL1 1
|
|
# define CONFIG_STM32_TIM4_CH1MODE CONFIG_STM32_TIM4_CHMODE
|
|
# elif CONFIG_STM32_TIM4_CHANNEL == 2
|
|
# define CONFIG_STM32_TIM4_CHANNEL2 1
|
|
# define CONFIG_STM32_TIM4_CH2MODE CONFIG_STM32_TIM4_CHMODE
|
|
# elif CONFIG_STM32_TIM4_CHANNEL == 3
|
|
# define CONFIG_STM32_TIM4_CHANNEL3 1
|
|
# define CONFIG_STM32_TIM4_CH3MODE CONFIG_STM32_TIM4_CHMODE
|
|
# elif CONFIG_STM32_TIM4_CHANNEL == 4
|
|
# define CONFIG_STM32_TIM4_CHANNEL4 1
|
|
# define CONFIG_STM32_TIM4_CH4MODE CONFIG_STM32_TIM4_CHMODE
|
|
# else
|
|
# error "Unsupported value of CONFIG_STM32_TIM4_CHANNEL"
|
|
# endif
|
|
# define PWM_TIM4_NCHANNELS 1
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM5_PWM
|
|
# if !defined(CONFIG_STM32_TIM5_CHANNEL)
|
|
# error "CONFIG_STM32_TIM5_CHANNEL must be provided"
|
|
# elif CONFIG_STM32_TIM5_CHANNEL == 1
|
|
# define CONFIG_STM32_TIM5_CHANNEL1 1
|
|
# define CONFIG_STM32_TIM5_CH1MODE CONFIG_STM32_TIM5_CHMODE
|
|
# elif CONFIG_STM32_TIM5_CHANNEL == 2
|
|
# define CONFIG_STM32_TIM5_CHANNEL2 1
|
|
# define CONFIG_STM32_TIM5_CH2MODE CONFIG_STM32_TIM5_CHMODE
|
|
# elif CONFIG_STM32_TIM5_CHANNEL == 3
|
|
# define CONFIG_STM32_TIM5_CHANNEL3 1
|
|
# define CONFIG_STM32_TIM5_CH3MODE CONFIG_STM32_TIM5_CHMODE
|
|
# elif CONFIG_STM32_TIM5_CHANNEL == 4
|
|
# define CONFIG_STM32_TIM5_CHANNEL4 1
|
|
# define CONFIG_STM32_TIM5_CH4MODE CONFIG_STM32_TIM5_CHMODE
|
|
# else
|
|
# error "Unsupported value of CONFIG_STM32_TIM5_CHANNEL"
|
|
# endif
|
|
# define PWM_TIM5_NCHANNELS 1
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM8_PWM
|
|
# if !defined(CONFIG_STM32_TIM8_CHANNEL)
|
|
# error "CONFIG_STM32_TIM8_CHANNEL must be provided"
|
|
# elif CONFIG_STM32_TIM8_CHANNEL == 1
|
|
# define CONFIG_STM32_TIM8_CHANNEL1 1
|
|
# define CONFIG_STM32_TIM8_CH1MODE CONFIG_STM32_TIM8_CHMODE
|
|
# elif CONFIG_STM32_TIM8_CHANNEL == 2
|
|
# define CONFIG_STM32_TIM8_CHANNEL2 1
|
|
# define CONFIG_STM32_TIM8_CH2MODE CONFIG_STM32_TIM8_CHMODE
|
|
# elif CONFIG_STM32_TIM8_CHANNEL == 3
|
|
# define CONFIG_STM32_TIM8_CHANNEL3 1
|
|
# define CONFIG_STM32_TIM8_CH3MODE CONFIG_STM32_TIM8_CHMODE
|
|
# elif CONFIG_STM32_TIM8_CHANNEL == 4
|
|
# define CONFIG_STM32_TIM8_CHANNEL4 1
|
|
# define CONFIG_STM32_TIM8_CH4MODE CONFIG_STM32_TIM8_CHMODE
|
|
# else
|
|
# error "Unsupported value of CONFIG_STM32_TIM8_CHANNEL"
|
|
# endif
|
|
# define PWM_TIM8_NCHANNELS 1
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM9_PWM
|
|
# if !defined(CONFIG_STM32_TIM9_CHANNEL)
|
|
# error "CONFIG_STM32_TIM9_CHANNEL must be provided"
|
|
# elif CONFIG_STM32_TIM9_CHANNEL == 1
|
|
# define CONFIG_STM32_TIM9_CHANNEL1 1
|
|
# define CONFIG_STM32_TIM9_CH1MODE CONFIG_STM32_TIM9_CHMODE
|
|
# elif CONFIG_STM32_TIM9_CHANNEL == 2
|
|
# define CONFIG_STM32_TIM9_CHANNEL2 1
|
|
# define CONFIG_STM32_TIM9_CH2MODE CONFIG_STM32_TIM9_CHMODE
|
|
# else
|
|
# error "Unsupported value of CONFIG_STM32_TIM9_CHANNEL"
|
|
# endif
|
|
# define PWM_TIM9_NCHANNELS 1
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM10_PWM
|
|
# if !defined(CONFIG_STM32_TIM10_CHANNEL)
|
|
# error "CONFIG_STM32_TIM10_CHANNEL must be provided"
|
|
# elif CONFIG_STM32_TIM10_CHANNEL == 1
|
|
# define CONFIG_STM32_TIM10_CHANNEL1 1
|
|
# define CONFIG_STM32_TIM10_CH1MODE CONFIG_STM32_TIM10_CHMODE
|
|
# else
|
|
# error "Unsupported value of CONFIG_STM32_TIM10_CHANNEL"
|
|
# endif
|
|
# define PWM_TIM10_NCHANNELS 1
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM11_PWM
|
|
# if !defined(CONFIG_STM32_TIM11_CHANNEL)
|
|
# error "CONFIG_STM32_TIM11_CHANNEL must be provided"
|
|
# elif CONFIG_STM32_TIM11_CHANNEL == 1
|
|
# define CONFIG_STM32_TIM11_CHANNEL1 1
|
|
# define CONFIG_STM32_TIM11_CH1MODE CONFIG_STM32_TIM11_CHMODE
|
|
# else
|
|
# error "Unsupported value of CONFIG_STM32_TIM11_CHANNEL"
|
|
# endif
|
|
# define PWM_TIM11_NCHANNELS 1
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM12_PWM
|
|
# if !defined(CONFIG_STM32_TIM12_CHANNEL)
|
|
# error "CONFIG_STM32_TIM12_CHANNEL must be provided"
|
|
# elif CONFIG_STM32_TIM12_CHANNEL == 1
|
|
# define CONFIG_STM32_TIM12_CHANNEL1 1
|
|
# define CONFIG_STM32_TIM12_CH1MODE CONFIG_STM32_TIM12_CHMODE
|
|
# elif CONFIG_STM32_TIM12_CHANNEL == 2
|
|
# define CONFIG_STM32_TIM12_CHANNEL2 1
|
|
# define CONFIG_STM32_TIM12_CH2MODE CONFIG_STM32_TIM12_CHMODE
|
|
# else
|
|
# error "Unsupported value of CONFIG_STM32_TIM12_CHANNEL"
|
|
# endif
|
|
# define PWM_TIM12_NCHANNELS 1
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM13_PWM
|
|
# if !defined(CONFIG_STM32_TIM13_CHANNEL)
|
|
# error "CONFIG_STM32_TIM13_CHANNEL must be provided"
|
|
# elif CONFIG_STM32_TIM13_CHANNEL == 1
|
|
# define CONFIG_STM32_TIM13_CHANNEL1 1
|
|
# define CONFIG_STM32_TIM13_CH1MODE CONFIG_STM32_TIM13_CHMODE
|
|
# else
|
|
# error "Unsupported value of CONFIG_STM32_TIM13_CHANNEL"
|
|
# endif
|
|
# define PWM_TIM13_NCHANNELS 1
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM14_PWM
|
|
# if !defined(CONFIG_STM32_TIM14_CHANNEL)
|
|
# error "CONFIG_STM32_TIM14_CHANNEL must be provided"
|
|
# elif CONFIG_STM32_TIM14_CHANNEL == 1
|
|
# define CONFIG_STM32_TIM14_CHANNEL1 1
|
|
# define CONFIG_STM32_TIM14_CH1MODE CONFIG_STM32_TIM14_CHMODE
|
|
# else
|
|
# error "Unsupported value of CONFIG_STM32_TIM14_CHANNEL"
|
|
# endif
|
|
# define PWM_TIM14_NCHANNELS 1
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM15_PWM
|
|
# if !defined(CONFIG_STM32_TIM15_CHANNEL)
|
|
# error "CONFIG_STM32_TIM15_CHANNEL must be provided"
|
|
# elif CONFIG_STM32_TIM15_CHANNEL == 1
|
|
# define CONFIG_STM32_TIM15_CHANNEL1 1
|
|
# define CONFIG_STM32_TIM15_CH1MODE CONFIG_STM32_TIM15_CHMODE
|
|
# elif CONFIG_STM32_TIM15_CHANNEL == 2
|
|
# define CONFIG_STM32_TIM15_CHANNEL2 1
|
|
# define CONFIG_STM32_TIM15_CH2MODE CONFIG_STM32_TIM15_CHMODE
|
|
# else
|
|
# error "Unsupported value of CONFIG_STM32_TIM15_CHANNEL"
|
|
# endif
|
|
# define PWM_TIM15_NCHANNELS 1
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM16_PWM
|
|
# if !defined(CONFIG_STM32_TIM16_CHANNEL)
|
|
# error "CONFIG_STM32_TIM16_CHANNEL must be provided"
|
|
# elif CONFIG_STM32_TIM16_CHANNEL == 1
|
|
# define CONFIG_STM32_TIM16_CHANNEL1 1
|
|
# define CONFIG_STM32_TIM16_CH1MODE CONFIG_STM32_TIM16_CHMODE
|
|
# else
|
|
# error "Unsupported value of CONFIG_STM32_TIM16_CHANNEL"
|
|
# endif
|
|
# define PWM_TIM16_NCHANNELS 1
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM17_PWM
|
|
# if !defined(CONFIG_STM32_TIM17_CHANNEL)
|
|
# error "CONFIG_STM32_TIM17_CHANNEL must be provided"
|
|
# elif CONFIG_STM32_TIM17_CHANNEL == 1
|
|
# define CONFIG_STM32_TIM17_CHANNEL1 1
|
|
# define CONFIG_STM32_TIM17_CH1MODE CONFIG_STM32_TIM17_CHMODE
|
|
# else
|
|
# error "Unsupported value of CONFIG_STM32_TIM17_CHANNEL"
|
|
# endif
|
|
# define PWM_TIM17_NCHANNELS 1
|
|
#endif
|
|
|
|
#endif /* CONFIG_PWM_MULTICHAN */
|
|
|
|
#ifdef CONFIG_STM32_TIM1_CH1OUT
|
|
# define PWM_TIM1_CH1CFG GPIO_TIM1_CH1OUT
|
|
#else
|
|
# define PWM_TIM1_CH1CFG 0
|
|
#endif
|
|
#ifdef CONFIG_STM32_TIM1_CH1NOUT
|
|
# define PWM_TIM1_CH1NCFG GPIO_TIM1_CH1NOUT
|
|
#else
|
|
# define PWM_TIM1_CH1NCFG 0
|
|
#endif
|
|
#ifdef CONFIG_STM32_TIM1_CH2OUT
|
|
# define PWM_TIM1_CH2CFG GPIO_TIM1_CH2OUT
|
|
#else
|
|
# define PWM_TIM1_CH2CFG 0
|
|
#endif
|
|
#ifdef CONFIG_STM32_TIM1_CH2NOUT
|
|
# define PWM_TIM1_CH2NCFG GPIO_TIM1_CH2NOUT
|
|
#else
|
|
# define PWM_TIM1_CH2NCFG 0
|
|
#endif
|
|
#ifdef CONFIG_STM32_TIM1_CH3OUT
|
|
# define PWM_TIM1_CH3CFG GPIO_TIM1_CH3OUT
|
|
#else
|
|
# define PWM_TIM1_CH3CFG 0
|
|
#endif
|
|
#ifdef CONFIG_STM32_TIM1_CH3NOUT
|
|
# define PWM_TIM1_CH3NCFG GPIO_TIM1_CH3NOUT
|
|
#else
|
|
# define PWM_TIM1_CH3NCFG 0
|
|
#endif
|
|
#ifdef CONFIG_STM32_TIM1_CH4OUT
|
|
# define PWM_TIM1_CH4CFG GPIO_TIM1_CH4OUT
|
|
#else
|
|
# define PWM_TIM1_CH4CFG 0
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM2_CH1OUT
|
|
# define PWM_TIM2_CH1CFG GPIO_TIM2_CH1OUT
|
|
#else
|
|
# define PWM_TIM2_CH1CFG 0
|
|
#endif
|
|
#ifdef CONFIG_STM32_TIM2_CH2OUT
|
|
# define PWM_TIM2_CH2CFG GPIO_TIM2_CH2OUT
|
|
#else
|
|
# define PWM_TIM2_CH2CFG 0
|
|
#endif
|
|
#ifdef CONFIG_STM32_TIM2_CH3OUT
|
|
# define PWM_TIM2_CH3CFG GPIO_TIM2_CH3OUT
|
|
#else
|
|
# define PWM_TIM2_CH3CFG 0
|
|
#endif
|
|
#ifdef CONFIG_STM32_TIM2_CH4OUT
|
|
# define PWM_TIM2_CH4CFG GPIO_TIM2_CH4OUT
|
|
#else
|
|
# define PWM_TIM2_CH4CFG 0
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM3_CH1OUT
|
|
# define PWM_TIM3_CH1CFG GPIO_TIM3_CH1OUT
|
|
#else
|
|
# define PWM_TIM3_CH1CFG 0
|
|
#endif
|
|
#ifdef CONFIG_STM32_TIM3_CH2OUT
|
|
# define PWM_TIM3_CH2CFG GPIO_TIM3_CH2OUT
|
|
#else
|
|
# define PWM_TIM3_CH2CFG 0
|
|
#endif
|
|
#ifdef CONFIG_STM32_TIM3_CH3OUT
|
|
# define PWM_TIM3_CH3CFG GPIO_TIM3_CH3OUT
|
|
#else
|
|
# define PWM_TIM3_CH3CFG 0
|
|
#endif
|
|
#ifdef CONFIG_STM32_TIM3_CH4OUT
|
|
# define PWM_TIM3_CH4CFG GPIO_TIM3_CH4OUT
|
|
#else
|
|
# define PWM_TIM3_CH4CFG 0
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM4_CH1OUT
|
|
# define PWM_TIM4_CH1CFG GPIO_TIM4_CH1OUT
|
|
#else
|
|
# define PWM_TIM4_CH1CFG 0
|
|
#endif
|
|
#ifdef CONFIG_STM32_TIM4_CH2OUT
|
|
# define PWM_TIM4_CH2CFG GPIO_TIM4_CH2OUT
|
|
#else
|
|
# define PWM_TIM4_CH2CFG 0
|
|
#endif
|
|
#ifdef CONFIG_STM32_TIM4_CH3OUT
|
|
# define PWM_TIM4_CH3CFG GPIO_TIM4_CH3OUT
|
|
#else
|
|
# define PWM_TIM4_CH3CFG 0
|
|
#endif
|
|
#ifdef CONFIG_STM32_TIM4_CH4OUT
|
|
# define PWM_TIM4_CH4CFG GPIO_TIM4_CH4OUT
|
|
#else
|
|
# define PWM_TIM4_CH4CFG 0
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM5_CH1OUT
|
|
# define PWM_TIM5_CH1CFG GPIO_TIM5_CH1OUT
|
|
#else
|
|
# define PWM_TIM5_CH1CFG 0
|
|
#endif
|
|
#ifdef CONFIG_STM32_TIM5_CH2OUT
|
|
# define PWM_TIM5_CH2CFG GPIO_TIM5_CH2OUT
|
|
#else
|
|
# define PWM_TIM5_CH2CFG 0
|
|
#endif
|
|
#ifdef CONFIG_STM32_TIM5_CH3OUT
|
|
# define PWM_TIM5_CH3CFG GPIO_TIM5_CH3OUT
|
|
#else
|
|
# define PWM_TIM5_CH3CFG 0
|
|
#endif
|
|
#ifdef CONFIG_STM32_TIM5_CH4OUT
|
|
# define PWM_TIM5_CH4CFG GPIO_TIM5_CH4OUT
|
|
#else
|
|
# define PWM_TIM5_CH4CFG 0
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM8_CH1OUT
|
|
# define PWM_TIM8_CH1CFG GPIO_TIM8_CH1OUT
|
|
#else
|
|
# define PWM_TIM8_CH1CFG 0
|
|
#endif
|
|
#ifdef CONFIG_STM32_TIM8_CH1NOUT
|
|
# define PWM_TIM8_CH1NCFG GPIO_TIM8_CH1NOUT
|
|
#else
|
|
# define PWM_TIM8_CH1NCFG 0
|
|
#endif
|
|
#ifdef CONFIG_STM32_TIM8_CH2OUT
|
|
# define PWM_TIM8_CH2CFG GPIO_TIM8_CH2OUT
|
|
#else
|
|
# define PWM_TIM8_CH2CFG 0
|
|
#endif
|
|
#ifdef CONFIG_STM32_TIM8_CH2NOUT
|
|
# define PWM_TIM8_CH2NCFG GPIO_TIM8_CH2NOUT
|
|
#else
|
|
# define PWM_TIM8_CH2NCFG 0
|
|
#endif
|
|
#ifdef CONFIG_STM32_TIM8_CH3OUT
|
|
# define PWM_TIM8_CH3CFG GPIO_TIM8_CH3OUT
|
|
#else
|
|
# define PWM_TIM8_CH3CFG 0
|
|
#endif
|
|
#ifdef CONFIG_STM32_TIM8_CH3NOUT
|
|
# define PWM_TIM8_CH3NCFG GPIO_TIM8_CH3NOUT
|
|
#else
|
|
# define PWM_TIM8_CH3NCFG 0
|
|
#endif
|
|
#ifdef CONFIG_STM32_TIM8_CH4OUT
|
|
# define PWM_TIM8_CH4CFG GPIO_TIM8_CH4OUT
|
|
#else
|
|
# define PWM_TIM8_CH4CFG 0
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM9_CH1OUT
|
|
# define PWM_TIM9_CH1CFG GPIO_TIM9_CH1OUT
|
|
#else
|
|
# define PWM_TIM9_CH1CFG 0
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM9_CH2OUT
|
|
# define PWM_TIM9_CH2CFG GPIO_TIM9_CH2OUT
|
|
#else
|
|
# define PWM_TIM9_CH2CFG 0
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM10_CH1OUT
|
|
# define PWM_TIM10_CH1CFG GPIO_TIM10_CH1OUT
|
|
#else
|
|
# define PWM_TIM10_CH1CFG 0
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM11_CH1OUT
|
|
# define PWM_TIM11_CH1CFG GPIO_TIM11_CH1OUT
|
|
#else
|
|
# define PWM_TIM11_CH1CFG 0
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM12_CH1OUT
|
|
# define PWM_TIM12_CH1CFG GPIO_TIM12_CH1OUT
|
|
#else
|
|
# define PWM_TIM12_CH1CFG 0
|
|
#endif
|
|
#ifdef CONFIG_STM32_TIM12_CH2OUT
|
|
# define PWM_TIM12_CH2CFG GPIO_TIM12_CH2OUT
|
|
#else
|
|
# define PWM_TIM12_CH2CFG 0
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM13_CH1OUT
|
|
# define PWM_TIM13_CH1CFG GPIO_TIM13_CH1OUT
|
|
#else
|
|
# define PWM_TIM13_CH1CFG 0
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM14_CH1OUT
|
|
# define PWM_TIM14_CH1CFG GPIO_TIM14_CH1OUT
|
|
#else
|
|
# define PWM_TIM14_CH1CFG 0
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM15_CH1OUT
|
|
# define PWM_TIM15_CH1CFG GPIO_TIM15_CH1OUT
|
|
#else
|
|
# define PWM_TIM15_CH1CFG 0
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM15_CH1NOUT
|
|
# define PWM_TIM15_CH1NCFG GPIO_TIM15_CH1NOUT
|
|
#else
|
|
# define PWM_TIM15_CH1NCFG 0
|
|
#endif
|
|
#ifdef CONFIG_STM32_TIM15_CH2OUT
|
|
# define PWM_TIM15_CH2CFG GPIO_TIM15_CH2OUT
|
|
#else
|
|
# define PWM_TIM15_CH2CFG 0
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM16_CH1OUT
|
|
# define PWM_TIM16_CH1CFG GPIO_TIM16_CH1OUT
|
|
#else
|
|
# define PWM_TIM16_CH1CFG 0
|
|
#endif
|
|
#ifdef CONFIG_STM32_TIM16_CH1NOUT
|
|
# define PWM_TIM16_CH1NCFG GPIO_TIM16_CH1NOUT
|
|
#else
|
|
# define PWM_TIM16_CH1NCFG 0
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_TIM17_CH1OUT
|
|
# define PWM_TIM17_CH1CFG GPIO_TIM17_CH1OUT
|
|
#else
|
|
# define PWM_TIM17_CH1CFG 0
|
|
#endif
|
|
#ifdef CONFIG_STM32_TIM17_CH1NOUT
|
|
# define PWM_TIM17_CH1NCFG GPIO_TIM17_CH1NOUT
|
|
#else
|
|
# define PWM_TIM17_CH1NCFG 0
|
|
#endif
|
|
|
|
/* Low-level ops helpers ************************************************************/
|
|
|
|
/* NOTE: low-level ops accept pwm_lowerhalf_s as first argument, but llops access
|
|
* can be found in stm32_pwm_dev_s
|
|
*/
|
|
|
|
#define PWM_SETUP(dev) \
|
|
(dev)->ops->setup((FAR struct pwm_lowerhalf_s *)dev)
|
|
#define PWM_SHUTDOWN(dev) \
|
|
(dev)->ops->shutdown((FAR struct pwm_lowerhalf_s *)dev)
|
|
#define PWM_CCR_UPDATE(dev, index, ccr) \
|
|
(dev)->llops->ccr_update((FAR struct pwm_lowerhalf_s *)dev, index, ccr)
|
|
#define PWM_CCR_GET(dev, index) \
|
|
(dev)->llops->ccr_get((FAR struct pwm_lowerhalf_s *)dev, index)
|
|
#define PWM_ARR_UPDATE(dev, arr) \
|
|
(dev)->llops->arr_update((FAR struct pwm_lowerhalf_s *)dev, arr)
|
|
#define PWM_ARR_GET(dev) \
|
|
(dev)->llops->arr_get((FAR struct pwm_lowerhalf_s *)dev)
|
|
#define PWM_OUTPUTS_ENABLE(dev, out, state) \
|
|
(dev)->llops->outputs_enable((FAR struct pwm_lowerhalf_s *)dev, out, state)
|
|
#define PWM_SOFT_UPDATE(dev) \
|
|
(dev)->llops->soft_update((FAR struct pwm_lowerhalf_s *)dev)
|
|
#define PWM_CONFIGURE(dev) \
|
|
(dev)->llops->configure((FAR struct pwm_lowerhalf_s *)dev)
|
|
#define PWM_SOFT_BREAK(dev, state) \
|
|
(dev)->llops->soft_break((FAR struct pwm_lowerhalf_s *)dev, state)
|
|
#define PWM_FREQ_UPDATE(dev, freq) \
|
|
(dev)->llops->freq_update((FAR struct pwm_lowerhalf_s *)dev, freq)
|
|
#define PWM_TIM_ENABLE(dev, state) \
|
|
(dev)->llops->tim_enable((FAR struct pwm_lowerhalf_s *)dev, state)
|
|
#define PWM_DUMP_REGS(dev) \
|
|
(dev)->llops->dump_regs((FAR struct pwm_lowerhalf_s *)dev)
|
|
#define PWM_DT_UPDATE(dev, dt) \
|
|
(dev)->llops->dt_update((FAR struct pwm_lowerhalf_s *)dev, dt)
|
|
|
|
/************************************************************************************
|
|
* Public Types
|
|
************************************************************************************/
|
|
|
|
/* Timer mode */
|
|
|
|
enum stm32_pwm_tim_mode_e
|
|
{
|
|
STM32_TIMMODE_COUNTUP = 0,
|
|
STM32_TIMMODE_COUNTDOWN = 1,
|
|
STM32_TIMMODE_CENTER1 = 2,
|
|
STM32_TIMMODE_CENTER2 = 3,
|
|
STM32_TIMMODE_CENTER3 = 4,
|
|
};
|
|
|
|
/* Timer output polarity */
|
|
|
|
enum stm32_pwm_pol_e
|
|
{
|
|
STM32_POL_POS = 0,
|
|
STM32_POL_NEG = 1,
|
|
};
|
|
|
|
/* Timer output IDLE state */
|
|
|
|
enum stm32_pwm_idle_e
|
|
{
|
|
STM32_IDLE_INACTIVE = 0,
|
|
STM32_IDLE_ACTIVE = 1
|
|
};
|
|
|
|
/* PWM channel mode */
|
|
|
|
enum stm32_chan_mode_e
|
|
{
|
|
STM32_CHANMODE_PWM1 = 0,
|
|
STM32_CHANMODE_PWM2 = 1,
|
|
#ifdef HAVE_IP_TIMERS_V2
|
|
STM32_CHANMODE_COMBINED1 = 2,
|
|
STM32_CHANMODE_COMBINED2 = 3,
|
|
STM32_CHANMODE_ASYMMETRIC1 = 4,
|
|
STM32_CHANMODE_ASYMMETRIC2 = 5
|
|
#endif
|
|
};
|
|
|
|
/* Timer channel */
|
|
|
|
enum stm32_chan_e
|
|
{
|
|
STM32_CHAN1 = (1 << 0),
|
|
STM32_CHAN1N = (1 << 1),
|
|
STM32_CHAN2 = (1 << 2),
|
|
STM32_CHAN2N = (1 << 3),
|
|
STM32_CHAN3 = (1 << 4),
|
|
STM32_CHAN3N = (1 << 5),
|
|
STM32_CHAN4 = (1 << 6),
|
|
/* No complementary output for CH4 */
|
|
#ifdef HAVE_IP_TIMERS_V2
|
|
/* Only available inside micro */
|
|
|
|
STM32_CHAN5 = (1 << 7),
|
|
/* 1<<8 reserved */
|
|
STM32_CHAN6 = (1 << 9),
|
|
/* 1<<10 reserved */
|
|
#endif
|
|
};
|
|
|
|
#ifdef CONFIG_STM32_PWM_LL_OPS
|
|
|
|
/* This structure provides the publicly visable representation of the
|
|
* "lower-half" PWM driver structure.
|
|
*/
|
|
|
|
struct stm32_pwm_dev_s
|
|
{
|
|
/* The first field of this state structure must be a pointer to the PWM
|
|
* callback structure to be consistent with upper-half PWM driver.
|
|
*/
|
|
|
|
FAR const struct pwm_ops_s *ops;
|
|
|
|
/* Publicly visible portion of the "lower-half" PWM driver structure */
|
|
|
|
FAR const struct stm32_pwm_ops_s *llops;
|
|
|
|
/* Require cast-compatibility with private "lower-half" PWM strucutre */
|
|
};
|
|
|
|
/* Low-level operations for PWM */
|
|
|
|
struct pwm_lowerhalf_s;
|
|
struct stm32_pwm_ops_s
|
|
{
|
|
/* Update CCR register */
|
|
|
|
int (*ccr_update)(FAR struct pwm_lowerhalf_s *dev, uint8_t index, uint32_t ccr);
|
|
|
|
/* Get CCR register */
|
|
|
|
uint32_t (*ccr_get)(FAR struct pwm_lowerhalf_s *dev, uint8_t index);
|
|
|
|
/* Update ARR register */
|
|
|
|
int (*arr_update)(FAR struct pwm_lowerhalf_s *dev, uint32_t arr);
|
|
|
|
/* Get ARR register */
|
|
|
|
uint32_t (*arr_get)(FAR struct pwm_lowerhalf_s *dev);
|
|
|
|
/* Enable outputs */
|
|
|
|
int (*outputs_enable)(FAR struct pwm_lowerhalf_s *dev, uint16_t outputs, bool state);
|
|
|
|
/* Software update */
|
|
|
|
int (*soft_update)(FAR struct pwm_lowerhalf_s *dev);
|
|
|
|
/* PWM configure */
|
|
|
|
int (*configure)(FAR struct pwm_lowerhalf_s *dev);
|
|
|
|
/* Software break */
|
|
|
|
int (*soft_break)(FAR struct pwm_lowerhalf_s *dev, bool state);
|
|
|
|
/* Update frequency */
|
|
|
|
int (*freq_update)(FAR struct pwm_lowerhalf_s *dev, uint32_t frequency);
|
|
|
|
/* Enable timer counter */
|
|
|
|
int (*tim_enable)(FAR struct pwm_lowerhalf_s *dev, bool state);
|
|
|
|
#ifdef CONFIG_DEBUG_PWM_INFO
|
|
/* Dump timer registers */
|
|
|
|
int (*dump_regs)(FAR struct pwm_lowerhalf_s *dev);
|
|
#endif
|
|
|
|
#ifdef HAVE_COMPLEMENTARY
|
|
/* Deadtime update */
|
|
|
|
int (*dt_update)(FAR struct pwm_lowerhalf_s *dev, uint8_t dt);
|
|
#endif
|
|
};
|
|
|
|
#endif /* CONFIG_STM32_PWM_LL_OPS */
|
|
|
|
/************************************************************************************
|
|
* Public Data
|
|
************************************************************************************/
|
|
|
|
#ifndef __ASSEMBLY__
|
|
|
|
#undef EXTERN
|
|
#if defined(__cplusplus)
|
|
#define EXTERN extern "C"
|
|
extern "C"
|
|
{
|
|
#else
|
|
#define EXTERN extern
|
|
#endif
|
|
|
|
/************************************************************************************
|
|
* Public Functions
|
|
************************************************************************************/
|
|
|
|
/************************************************************************************
|
|
* Name: stm32_pwminitialize
|
|
*
|
|
* Description:
|
|
* Initialize one timer for use with the upper_level PWM driver.
|
|
*
|
|
* Input Parameters:
|
|
* timer - A number identifying the timer use. The number of valid timer
|
|
* IDs varies with the STM32 MCU and MCU family but is somewhere in
|
|
* the range of {1,..,17}.
|
|
*
|
|
* Returned Value:
|
|
* On success, a pointer to the STM32 lower half PWM driver is returned.
|
|
* NULL is returned on any failure.
|
|
*
|
|
************************************************************************************/
|
|
|
|
FAR struct pwm_lowerhalf_s *stm32_pwminitialize(int timer);
|
|
|
|
#undef EXTERN
|
|
#if defined(__cplusplus)
|
|
}
|
|
#endif
|
|
|
|
#endif /* __ASSEMBLY__ */
|
|
#endif /* CONFIG_STM32_TIMx_PWM */
|
|
#endif /* __ARCH_ARM_SRC_STM32_STM32_PWM_H */
|