420 lines
21 KiB
C
420 lines
21 KiB
C
/************************************************************************************
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* arch/arm/src/lpc31xx/lpc31_memorymap.h
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*
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* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_LPC31XX_LPC31_MEMORYMAP_H
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#define __ARCH_ARM_SRC_LPC31XX_LPC31_MEMORYMAP_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* LPC31XX Physical (unmapped) Memory Map */
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#define LPC31_FIRST_PSECTION 0x00000000 /* Beginning of the physical address space */
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#define LPC31_SHADOWSPACE_PSECTION 0x00000000 /* 0x00000000-0x00000fff: Shadow Area 4Kb */
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/* 0x00001000-0xff027fff: Reserved */
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#define LPC31_INTSRAM_PSECTION 0x11028000 /* Internal SRAM 0+1 192Kb */
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# define LPC31_INTSRAM0_PADDR 0x11028000 /* 0x11028000-0x1103ffff: Internal SRAM 0 96Kb */
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# define LPC31_INTSRAM1_PADDR 0x11040000 /* 0x11040000-0x11057fff: Internal SRAM 1 96Kb */
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/* 0x11058000-11ffffffff: Reserved */
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#define LPC31_INTSROM0_PSECTION 0x12000000 /* 0x12000000-0x1201ffff: Internal SROM 0 128Kb */
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/* 0x12020000-0x12ffffff: Reserved */
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#define LPC31_APB01_PSECTION 0x13000000 /* 0x13000000-0x1300bfff: APB0 32Kb APB1 16Kb */
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# define LPC31_APB0_PADDR 0x13000000 /* 0x13000000-0x13007fff: APB0 32Kb */
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# define LPC31_APB1_PADDR 0x13008000 /* 0x13008000-0x1300bfff: APB1 16Kb */
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/* 0x1300c000-0x14ffffff: Reserved */
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#define LPC31_APB2_PSECTION 0x15000000 /* 0x15000000-0x15003fff: APB2 16Kb */
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#define LPC31_APB3_PSECTION 0x16000000 /* 0x16000000-0x160003ff: APB3 1Kb */
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#define LPC31_APB4MPMC_PSECTION 0x17000000 /* 8Kb */
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# define LPC31_APB4_PADDR 0x17000000 /* 0x17000000-0x17000fff: APB4 4Kb */
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# define LPC31_MPMC_PADDR 0x17008000 /* 0x17008000-0x17008fff: MPMC cfg 4Kb */
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/* 0x17009000-0x17ffffff: Reserved */
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#define LPC31_MCI_PSECTION 0x18000000 /* 0x18000000 0x180003ff: MCI/SD/SDIO 1Kb */
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/* 0x18000900-0x18ffffff: Reserved */
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#define LPC31_USBOTG_PSECTION 0x19000000 /* 0x19000000-0x19000fff: USB OTG 4Kb */
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/* 0x19001000-0x1fffffff: Reserved */
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#define LPC31_EXTSRAM_PSECTION 0x20000000 /* 64-128Kb */
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# define LPC31_EXTSRAM0_PADDR 0x20000000 /* 0x20000000-0x2001ffff: External SRAM 0 64-128Kb */
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# define LPC31_EXTSRAM1_PADDR 0x20020000 /* 0x20020000-0x2003ffff: External SRAM 1 64-128Kb */
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#define LPC31_EXTSDRAM0_PSECTION 0x30000000 /* 0x30000000-0x37ffffff: External SDRAM 0 128Mb */
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/* 0x40000000-0x5fffffff: Reserved */
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#define LPC31_INTC_PSECTION 0x60000000 /* 0x60000000-0x60000fff: Interrupt controller 4Kb */
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/* 0x60001000-0x6fffffff: Reserved */
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#define LPC31_NAND_PSECTION 0x70000000 /* 0x70000000-0x700007ff: NANDFLASH Ctrl 2Kb */
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/* 0x70000800-0xffffffff: Reserved */
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#ifdef CONFIG_LPC31_EXTNAND /* End of the physical address space */
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# define LPC31_LAST_PSECTION (LPC31_NAND_PSECTION + (1 << 20))
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#else
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# define LPC31_LAST_PSECTION (LPC31_INTC_PSECTION + (1 << 20))
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#endif
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/* APB0-4 Domain Offsets */
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#define LPC31_APB0_EVNTRTR_OFFSET 0x00000000 /* Event Router */
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#define LPC31_APB0_ADC_OFFSET 0x00002000 /* ADC 10-bit */
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#define LPC31_APB0_WDT_OFFSET 0x00002400 /* WDT */
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#define LPC31_APB0_SYSCREG_OFFSET 0x00002800 /* SYSCREG block */
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#define LPC31_APB0_IOCONFIG_OFFSET 0x00003000 /* IOCONFIG */
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#define LPC31_APB0_GCU_OFFSET 0x00004000 /* GCU */
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#define LPC31_APB0_OTP_OFFSET 0x00005000 /* USB OTP (LPC315x only) */
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#define LPC31_APB0_RNG_OFFSET 0x00006000 /* RNG */
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#define LPC31_APB1_TIMER0_OFFSET 0x00000000 /* TIMER0 */
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#define LPC31_APB1_TIMER1_OFFSET 0x00000400 /* TIMER1 */
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#define LPC31_APB1_TIMER2_OFFSET 0x00000800 /* TIMER2 */
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#define LPC31_APB1_TIMER3_OFFSET 0x00000c00 /* TIMER3 */
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#define LPC31_APB1_PWM_OFFSET 0x00001000 /* PWM */
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#define LPC31_APB1_I2C0_OFFSET 0x00002000 /* I2C0 */
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#define LPC31_APB1_I2C1_OFFSET 0x00002400 /* I2C1 */
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#define LPC31_APB2_PCM_OFFSET 0x00000000 /* PCM */
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#define LPC31_APB2_LCD_OFFSET 0x00000400 /* LCD */
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/* 0x00000800 Reserved */
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#define LPC31_APB2_UART_OFFSET 0x00001000 /* UART */
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#define LPC31_APB2_SPI_OFFSET 0x00002000 /* SPI */
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/* 0x00003000 Reserved */
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#define LPC31_APB3_I2SCONFIG_OFFSET 0x00000000 /* I2S System Configuration */
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#define LPC31_APB3_I2STX0_OFFSET 0x00000080 /* I2S TX0 */
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#define LPC31_APB3_I2STX1_OFFSET 0x00000100 /* I2S TX1 */
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#define LPC31_APB3_I2SRX0_OFFSET 0x00000180 /* I2S RX0 */
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#define LPC31_APB3_I2SRX1_OFFSET 0x00000200 /* I2S RX1 */
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/* 0x00000280 Reserved */
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#define LPC31_APB4_DMA_OFFSET 0x00000000 /* DMA */
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#define LPC31_APB4_NAND_OFFSET 0x00000800 /* NAND FLASH Controller */
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/* 0x00001000 Reserved */
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/* Sizes of memory regions in bytes */
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#define LPC31_SHADOWSPACE_SIZE (4*1024)
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#define LPC31_INTSRAM0_SIZE (96*1024)
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#define LPC31_INTSRAM1_SIZE (96*1024)
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#define LPC31_INTSROM0_SIZE (128*1024)
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#define LPC31_APB0_SIZE (32*1024)
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#define LPC31_APB1_SIZE (16*1024)
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#define LPC31_APB2_SIZE (16*1024)
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#define LPC31_APB3_SIZE (1*1024)
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#define LPC31_APB4_SIZE (4*1024)
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#define LPC31_MPMC_SIZE (4*1024)
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#define LPC31_APB4MPMC_SIZE (LPC31_APB4_SIZE+LPC31_MPMC_SIZE)
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#define LPC31_MCI_SIZE (1*1024)
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#define LPC31_USBOTG_SIZE (4*1024)
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#define LPC31_INTC_SIZE (4*1024)
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#define LPC31_NAND_SIZE (2*1024)
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#ifdef HAVE_INTSRAM1
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# define LPC31_ISRAM_SIZE (LPC31_INTSRAM0_SIZE+LPC31_INTSRAM1_SIZE)
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#else
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# define LPC31_ISRAM_SIZE LPC31_INTSRAM0_SIZE
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#endif
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/* Convert size in bytes to number of sections (in Mb). */
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#define _NSECTIONS(b) (((b)+0x000fffff) >> 20)
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/* Sizes of sections/regions. The boot logic in lpc31_boot.c, will select
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* 1Mb level 1 MMU mappings to span the entire physical address space.
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* The definitions below specify the number of 1Mb entries that are
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* required to span a particular address region.
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*/
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#define LPC31_SHADOWSPACE_NSECTIONS 1 /* 4Kb - <1 section */
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#define LPC31_INTSRAM_NSECTIONS 1 /* 96 or 192Kb - <1 section */
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#define LPC31_APB01_NSECTIONS 1 /* 32Kb - <1 section */
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#define LPC31_INTSROM0_NSECTIONS 1 /* 128Kb - <1 section */
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#define LPC31_APB1_NSECTIONS 1 /* 16Kb - <1 section */
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#define LPC31_APB2_NSECTIONS 1 /* 16Kb - <1 section */
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#define LPC31_APB3_NSECTIONS 1 /* 1Kb - <1 section */
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#define LPC31_APB4MPMC_NSECTIONS 1 /* 8Kb - <1 section */
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#define LPC31_MCI_NSECTIONS 1 /* 1Kb - <1 section */
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#define LPC31_USBOTG_NSECTIONS 1 /* 4Kb - <1 section */
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#define LPC31_EXTSRAM_NSECTIONS 1 /* 64-128Kb - <1 section */
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#define LPC31_INTC_NSECTIONS 1 /* 4Kb - <1 section */
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#define LPC31_NAND_NSECTIONS 1 /* 2Kb - <1 section */
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/* External SDRAM is a special case -- the number of sections depends upon
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* the size of the SDRAM installed.
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*/
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#if defined(CONFIG_LPC31_EXTDRAM) && CONFIG_LPC31_EXTDRAMSIZE > 0
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# define LPC31_EXTSDRAM0_NSECTIONS _NSECTIONS(CONFIG_LPC31_EXTDRAMSIZE)
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#endif
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/* Section MMU Flags */
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#define LPC31_SHADOWSPACE_MMUFLAGS MMU_ROMFLAGS
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#define LPC31_INTSRAM_MMUFLAGS MMU_MEMFLAGS
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#define LPC31_INTSROM_MMUFLAGS MMU_MEMFLAGS
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#define LPC31_APB01_MMUFLAGS MMU_IOFLAGS
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#define LPC31_APB2_MMUFLAGS MMU_IOFLAGS
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#define LPC31_APB3_MMUFLAGS MMU_IOFLAGS
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#define LPC31_APB4MPMC_MMUFLAGS MMU_IOFLAGS
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#define LPC31_MCI_MMUFLAGS MMU_IOFLAGS
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#define LPC31_USBOTG_MMUFLAGS MMU_IOFLAGS
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#define LPC31_EXTSRAM_MMUFLAGS MMU_MEMFLAGS
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#define LPC31_EXTSDRAM_MMUFLAGS MMU_MEMFLAGS
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#define LPC31_INTC_MMUFLAGS MMU_IOFLAGS
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#define LPC31_NAND_MMUFLAGS MMU_IOFLAGS
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/* board_memorymap.h contains special mappings that are needed when a ROM
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* memory map is used. It is included in this odd location becaue it depends
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* on some the virtual address definitions provided above.
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*/
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#include <arch/board/board_memorymap.h>
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/* LPC31XX Virtual (mapped) Memory Map. These are the mappings that will
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* be created if the page table lies in RAM. If the platform has another,
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* read-only, pre-initialized page table (perhaps in ROM), then the board.h
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* file must provide these definitions.
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*/
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#ifndef CONFIG_ARCH_ROMPGTABLE
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# define LPC31_FIRST_VSECTION 0x00000000 /* Beginning of the virtual address space */
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# define LPC31_SHADOWSPACE_VSECTION 0x00000000 /* 0x00000000-0x00000fff: Shadow Area 4Kb */
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# define LPC31_INTSRAM_VSECTION 0x11028000 /* Internal SRAM 96Kb-192Kb */
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# define LPC31_INTSRAM0_VADDR 0x11028000 /* 0x11028000-0x1103ffff: Internal SRAM 0 96Kb */
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# define LPC31_INTSRAM1_VADDR 0x11040000 /* 0x11040000-0x11057fff: Internal SRAM 1 96Kb */
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# define LPC31_INTSROM0_VSECTION 0x12000000 /* 0x12000000-0x1201ffff: Internal SROM 0 128Kb */
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# define LPC31_APB01_VSECTION 0x13000000 /* 0x13000000-0x1300bfff: APB0 32Kb APB0 32Kb */
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# define LPC31_APB0_VADDR 0x13000000 /* 0x13000000-0x13007fff: APB0 32Kb */
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# define LPC31_APB1_VADDR 0x13008000 /* 0x13008000-0x1300bfff: APB1 16Kb */
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# define LPC31_APB2_VSECTION 0x15000000 /* 0x15000000-0x15003fff: APB2 16Kb */
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# define LPC31_APB3_VSECTION 0x16000000 /* 0x16000000-0x160003ff: APB3 1Kb */
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# define LPC31_APB4MPMC_VSECTION 0x17000000 /* 8Kb */
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# define LPC31_APB4_VADDR 0x17000000 /* 0x17000000-0x17000fff: APB4 4Kb */
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# define LPC31_MPMC_VADDR 0x17008000 /* 0x17008000-0x17008fff: MPMC cfg 4Kb */
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# define LPC31_MCI_VSECTION 0x18000000 /* 0x18000000 0x180003ff: MCI/SD/SDIO 1Kb */
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# define LPC31_USBOTG_VSECTION 0x19000000 /* 0x19000000-0x19000fff: USB OTG 4Kb */
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# define LPC31_EXTSRAM_VSECTION 0x20020000 /* 64-128Kb */
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# define LPC31_EXTSRAM0_VADDR 0x20000000 /* 0x20000000-0x2001ffff: External SRAM 0 64-128Kb */
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# define LPC31_EXTSRAM1_VADDR 0x20020000 /* 0x20020000-0x2003ffff: External SRAM 1 64-128Kb */
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# define LPC31_EXTSDRAM0_VSECTION 0x30000000 /* 0x30000000-0x37ffffff: External SDRAM 0 128Mb */
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# define LPC31_INTC_VSECTION 0x60000000 /* 0x60000000-0x60000fff: Interrupt controller 4Kb */
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# define LPC31_NAND_VSECTION 0x70000000 /* 0x70000000-0x700007ff: NANDFLASH Ctrl 2Kb */
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#
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# ifdef CONFIG_LPC31_EXTNAND /* End of the virtual address space */
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# define LPC31_LAST_VSECTION (LPC31_NAND_VSECTION + (1 << 20))
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# else
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# define LPC31_LAST_VSECTION (LPC31_INTC_VSECTION + (1 << 20))
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# endif
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#endif
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/* The boot logic will create a temporarily mapping based on where NuttX is
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* executing in memory. In this case, NuttX could be running from NOR FLASH,
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* SDRAM, external SRAM, or ISRAM.
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*/
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#if defined(CONFIG_BOOT_RUNFROMFLASH)
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# define NUTTX_START_VADDR LPC31_MPMC_VADDR
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# define NUTTX_START_PADDR LPC31_MPMC_PADDR
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#elif defined(CONFIG_BOOT_RUNFROMSDRAM)
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# define NUTTX_START_VADDR LPC31_EXTSDRAM0_VSECTION
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# define NUTTX_START_PADDR LPC31_EXTSDRAM0_PSECTION
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#elif defined(CONFIG_BOOT_RUNFROMEXTSRAM)
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# define NUTTX_START_VADDR LPC31_EXTSRAM0_VADDR
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# define NUTTX_START_PADDR LPC31_EXTSRAM0_PADDR
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#else /* CONFIG_BOOT_RUNFROMISRAM, CONFIG_PAGING */
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# define NUTTX_START_VADDR LPC31_INTSRAM0_VADDR
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# define NUTTX_START_PADDR LPC31_INTSRAM0_PADDR
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#endif
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/* Determine the address of the MMU page table. We will try to place that page
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* table at the beginng of ISRAM0 if the vectors are at the high address, 0xffff:0000
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* or at the end of ISRAM1 (or ISRAM0 if ISRAM1 is not available in this architecture)
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* if the vectors are at 0x0000:0000
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*
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* Or... the user may specify the address of the page table explicitly be defining
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* PGTABLE_BASE_VADDR and PGTABLE_BASE_PADDR in the board.h file.
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*/
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#undef PGTABLE_IN_HIGHSRAM
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#undef PGTABLE_IN_LOWSRAM
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#if !defined(PGTABLE_BASE_PADDR) || !defined(PGTABLE_BASE_VADDR)
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/* Sanity check.. if one is undefined, both should be undefined */
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# if defined(PGTABLE_BASE_PADDR) || defined(PGTABLE_BASE_VADDR)
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# error "Only one of PGTABLE_BASE_PADDR or PGTABLE_BASE_VADDR is defined"
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# endif
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/* A sanity check, if the configuration says that the page table is read-only
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* and pre-initialized (maybe ROM), then it should have also defined both of
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* the page table base addresses.
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*/
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# ifdef CONFIG_ARCH_ROMPGTABLE
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# error "CONFIG_ARCH_ROMPGTABLE defined; PGTABLE_BASE_P/VADDR not defined"
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# else
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/* If CONFIG_PAGING is selected, then parts of the 1-to-1 virtual memory
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* map probably do not apply because paging logic will probably partition
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* the SRAM section differently. In particular, if the page table is located
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* at the end of SRAM, then the virtual page table address defined below
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* will probably be in error.
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*
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* We work around this header file interdependency by (1) insisting that
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* pg_macros.h be included AFTER this header file, then (2) allowing the
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* pg_macros.h header file to redefine PGTABLE_BASE_VADDR.
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*/
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# if defined(CONFIG_PAGING) && defined(__ARCH_ARM_SRC_ARM_PG_MACROS_H)
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# error "pg_macros.h must be included AFTER this header file"
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# endif
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/* We must declare the page table in ISRAM0 or 1. We decide depending upon
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* where the vector table was place.
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*/
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# ifdef CONFIG_ARCH_LOWVECTORS /* Vectors located at 0x0000:0000 */
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/* In this case, ISRAM0 will be shadowed at address 0x0000:0000. The page
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* table must lie at the top 16Kb of ISRAM1 (or ISRAM0 if this is a ISRAM1 is
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* not available in this architecture)
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*/
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# ifdef HAVE_INTSRAM1
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# define PGTABLE_BASE_PADDR (LPC31_INTSRAM1_PADDR+LPC31_INTSRAM1_SIZE-PGTABLE_SIZE)
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# define PGTABLE_BASE_VADDR (LPC31_INTSRAM1_VADDR+LPC31_INTSRAM1_SIZE-PGTABLE_SIZE)
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# else
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# define PGTABLE_BASE_PADDR (LPC31_INTSRAM0_PADDR+LPC31_INTSRAM0_SIZE-PGTABLE_SIZE)
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# define PGTABLE_BASE_VADDR (LPC31_INTSRAM0_VADDR+LPC31_INTSRAM0_SIZE-PGTABLE_SIZE)
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# endif
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# define PGTABLE_IN_HIGHSRAM 1
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/* If CONFIG_PAGING is defined, insist that pg_macros.h assign the virtual
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* address of the page table.
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*/
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# ifdef CONFIG_PAGING
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# undef PGTABLE_BASE_VADDR
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# endif
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# else
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/* Otherwise, ISRAM1 (or ISRAM0 for the is ISRAM1 is not available in this
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* architecture) will be mapped so that the end of the SRAM region will
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* provide memory for the vectors. The page table will then be places at
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* the first 16Kb of ISRAM0 (which will be in the shadow memory region).
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*/
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# define PGTABLE_BASE_PADDR LPC31_SHADOWSPACE_PSECTION
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# define PGTABLE_BASE_VADDR LPC31_SHADOWSPACE_VSECTION
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# define PGTABLE_IN_LOWSRAM 1
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# endif
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# endif
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#endif
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/* Page table start addresses:
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*
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* 16Kb of memory is reserved hold the page table for the virtual mappings. A
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* portion of this table is not accessible in the virtual address space (for
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* normal operation). We will reuse this memory for coarse page tables as follows:
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*
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* NOTE: If CONFIG_PAGING is defined, pg_macros.h will re-assign the virtual
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* address of the page table.
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*/
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#define PGTABLE_L2_COARSE_OFFSET ((((LPC31_LAST_PSECTION >> 20) + 255) & ~255) << 2)
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#define PGTABLE_L2_COARSE_PBASE (PGTABLE_BASE_PADDR+PGTABLE_L2_COARSE_OFFSET)
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#define PGTABLE_L2_COARSE_VBASE (PGTABLE_BASE_VADDR+PGTABLE_L2_COARSE_OFFSET)
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#define PGTABLE_L2_FINE_OFFSET ((((LPC31_LAST_PSECTION >> 20) + 1023) & ~1023) << 2)
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#define PGTABLE_L2_FINE_PBASE (PGTABLE_BASE_PADDR+PGTABLE_L2_FINE_OFFSET)
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#define PGTABLE_L2_FINE_VBASE (PGTABLE_BASE_VADDR+PGTABLE_L2_FINE_OFFSET)
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/* Page table end addresses: */
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#define PGTABLE_L2_END_PADDR (PGTABLE_BASE_PADDR+PGTABLE_SIZE)
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#define PGTABLE_L2_END_VADDR (PGTABLE_BASE_VADDR+PGTABLE_SIZE)
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/* Page table sizes */
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#define PGTABLE_L2_COARSE_ALLOC (PGTABLE_L2_END_VADDR-PGTABLE_L2_COARSE_VBASE)
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#define PGTABLE_COARSE_TABLE_SIZE (4*256)
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#define PGTABLE_NCOARSE_TABLES (PGTABLE_L2_COARSE_ALLOC / PGTABLE_COARSE_TABLE_SIZE)
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#define PGTABLE_L2_FINE_ALLOC (PGTABLE_L2_END_VADDR-PGTABLE_L2_FINE_VBASE)
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#define PGTABLE_FINE_TABLE_SIZE (4*1024)
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#define PGTABLE_NFINE_TABLES (PGTABLE_L2_FINE_ALLOC / PGTABLE_FINE_TABLE_SIZE)
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/* Determine the base address of the vector table:
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*
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* LPC31_VECTOR_PADDR - Unmapped, physical address of vector table in SRAM
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* LPC31_VECTOR_VSRAM - Virtual address of vector table in SRAM
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* LPC31_VECTOR_VADDR - Virtual address of vector table (0x00000000 or 0xffff0000)
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*/
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#define VECTOR_TABLE_SIZE 0x00010000
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#ifdef CONFIG_ARCH_LOWVECTORS /* Vectors located at 0x0000:0000 */
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# define LPC31_VECTOR_PADDR LPC31_INTSRAM0_PADDR
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# define LPC31_VECTOR_VSRAM LPC31_INTSRAM0_VADDR
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# define LPC31_VECTOR_VADDR 0x00000000
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# define LPC31_VECTOR_VCOARSE 0x00000000
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#else /* Vectors located at 0xffff:0000 -- this probably does not work */
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# ifdef HAVE_INTSRAM1
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# define LPC31_VECTOR_PADDR (LPC31_INTSRAM1_PADDR+LPC31_INTSRAM1_SIZE-VECTOR_TABLE_SIZE)
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# define LPC31_VECTOR_VSRAM (LPC31_INTSRAM1_VADDR+LPC31_INTSRAM1_SIZE-VECTOR_TABLE_SIZE)
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# else
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# define LPC31_VECTOR_PADDR (LPC31_INTSRAM0_PADDR+LPC31_INTSRAM0_SIZE-VECTOR_TABLE_SIZE)
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# define LPC31_VECTOR_VSRAM (LPC31_INTSRAM0_VADDR+LPC31_INTSRAM0_SIZE-VECTOR_TABLE_SIZE)
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# endif
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# define LPC31_VECTOR_VADDR 0xffff0000
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# define LPC31_VECTOR_VCOARSE 0xfff00000
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#endif
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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|
* Public Data
|
|
************************************************************************************/
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/************************************************************************************
|
|
* Public Functions
|
|
************************************************************************************/
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#endif /* __ARCH_ARM_SRC_LPC31XX_LPC31_MEMORYMAP_H */
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