nuttx/arch/risc-v
Ville Juven 7c2930c3df mpfs/mpfs_corespi: Optimize TX / RX FIFO handling
Remove unnecessary reading of the status register when loading / unloading
the FIFOs. Reading from the IP block is slow due to BUS synchronization and
this basically makes the SPI busy loop for no reason at all, destroying the
CPU usage.

The overall benefit of these changes is approx. 25%-points, which is a
MASSIVE improvement.
2023-05-31 15:52:56 -03:00
..
include arch/risc-v: change up_saveusercontext to assembly code 2023-04-27 17:34:30 +08:00
src mpfs/mpfs_corespi: Optimize TX / RX FIFO handling 2023-05-31 15:52:56 -03:00
Kconfig litex: Support for kernel build with vexriscv-smp. 2023-04-22 01:40:32 +08:00