zhangyuan21 806a2a8b8d arch/armv7-ar: flush dcache when addr is not aligned with cache line ... When invalidate address is not aligned with cache line, must align address and flush the cache line. Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>		2023-01-16 16:14:32 +08:00
..
include	arch/Kconfig: remove virtual memory allocator dependency from MM_SHM	2023-01-13 02:20:13 +08:00
src	arch/armv7-ar: flush dcache when addr is not aligned with cache line	2023-01-16 16:14:32 +08:00
Kconfig	arm/Kconfig: add cortex-m85 config	2022-12-09 01:53:10 +08:00