251 lines
15 KiB
C
251 lines
15 KiB
C
/****************************************************************************
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* arch/arm/src/lpc31xx/lpc31_uart.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_LPC31XX_LPC31_UART_H
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#define __ARCH_ARM_SRC_LPC31XX_LPC31_UART_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include "lpc31_memorymap.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* UART register base address offset into the APB2 domain *******************/
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#define LPC31_UART_VBASE (LPC31_APB2_VSECTION+LPC31_APB2_UART_OFFSET)
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#define LPC31_UART_PBASE (LPC31_APB2_PSECTION+LPC31_APB2_UART_OFFSET)
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/* UART register offsets (with respect to the UART base) ********************/
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#define LPC31_UART_RBR_OFFSET 0x000 /* Receiver Buffer Register */
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#define LPC31_UART_THR_OFFSET 0x000 /* Transmitter Holding Register */
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#define LPC31_UART_DLL_OFFSET 0x000 /* Divisor Latch LSB */
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#define LPC31_UART_DLM_OFFSET 0x004 /* Divisor Latch MSB */
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#define LPC31_UART_IER_OFFSET 0x004 /* Interrupt Enable Register */
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#define LPC31_UART_IIR_OFFSET 0x008 /* Interrupt Identification Register */
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#define LPC31_UART_FCR_OFFSET 0x008 /* FIFO Control Register */
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#define LPC31_UART_LCR_OFFSET 0x00c /* Line Control Register */
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#define LPC31_UART_MCR_OFFSET 0x010 /* Modem Control Register */
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#define LPC31_UART_LSR_OFFSET 0x014 /* Line Status Register */
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#define LPC31_UART_MSR_OFFSET 0x018 /* Modem status Register */
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#define LPC31_UART_SCR_OFFSET 0x01c /* Scratch Register */
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/* 0x020: Reserved */
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#define LPC31_UART_ICR_OFFSET 0x024 /* IrDA Control Register */
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#define LPC31_UART_FDR_OFFSET 0x028 /* Fractional Divider Register */
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/* 0x02c: Reserved */
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#define LPC31_UART_POP_OFFSET 0x030 /* NHP Pop Register */
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#define LPC31_UART_MODE_OFFSET 0x034 /* NHP Mode Selection Register */
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/* 0x038-0xfd4: Reserved */
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#define LPC31_UART_INTCE_OFFSET 0xfd8 /* Interrupt Clear Enable Register */
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#define LPC31_UART_INTSE_OFFSET 0xfdc /* Interrupt Set Enable Register */
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#define LPC31_UART_INTS_OFFSET 0xfe0 /* Interrupt Status Register */
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#define LPC31_UART_INTE_OFFSET 0xfe4 /* Interrupt Enable Register */
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#define LPC31_UART_INTCS_OFFSET 0xfe8 /* Interrupt Clear Status Register */
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#define LPC31_UART_INTSS_OFFSET 0xfec /* Interrupt Set Status Register */
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/* 0xff0-0xff8: Reserved */
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/* UART register (virtual) addresses ****************************************/
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#define LPC31_UART_RBR (LPC31_UART_VBASE+LPC31_UART_RBR_OFFSET)
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#define LPC31_UART_THR (LPC31_UART_VBASE+LPC31_UART_THR_OFFSET)
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#define LPC31_UART_DLL (LPC31_UART_VBASE+LPC31_UART_DLL_OFFSET)
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#define LPC31_UART_DLM (LPC31_UART_VBASE+LPC31_UART_DLM_OFFSET)
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#define LPC31_UART_IER (LPC31_UART_VBASE+LPC31_UART_IER_OFFSET)
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#define LPC31_UART_IIR (LPC31_UART_VBASE+LPC31_UART_IIR_OFFSET)
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#define LPC31_UART_FCR (LPC31_UART_VBASE+LPC31_UART_FCR_OFFSET)
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#define LPC31_UART_LCR (LPC31_UART_VBASE+LPC31_UART_LCR_OFFSET)
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#define LPC31_UART_MCR (LPC31_UART_VBASE+LPC31_UART_MCR_OFFSET)
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#define LPC31_UART_LSR (LPC31_UART_VBASE+LPC31_UART_LSR_OFFSET)
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#define LPC31_UART_MSR (LPC31_UART_VBASE+LPC31_UART_MSR_OFFSET)
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#define LPC31_UART_SCR (LPC31_UART_VBASE+LPC31_UART_SCR_OFFSET)
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#define LPC31_UART_ICR (LPC31_UART_VBASE+LPC31_UART_ICR_OFFSET)
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#define LPC31_UART_FDR (LPC31_UART_VBASE+LPC31_UART_FDR_OFFSET)
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#define LPC31_UART_POP (LPC31_UART_VBASE+LPC31_UART_POP_OFFSET)
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#define LPC31_UART_MODE (LPC31_UART_VBASE+LPC31_UART_MODE_OFFSET)
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#define LPC31_UART_INTCE (LPC31_UART_VBASE+LPC31_UART_INTCE_OFFSET)
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#define LPC31_UART_INTSE (LPC31_UART_VBASE+LPC31_UART_INTSE_OFFSET)
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#define LPC31_UART_INTS (LPC31_UART_VBASE+LPC31_UART_INTS_OFFSET)
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#define LPC31_UART_INTE (LPC31_UART_VBASE+LPC31_UART_INTE_OFFSET)
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#define LPC31_UART_INTCS (LPC31_UART_VBASE+LPC31_UART_INTCS_OFFSET)
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#define LPC31_UART_INTSS (LPC31_UART_VBASE+LPC31_UART_INTSS_OFFSET)
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/* UART register bit definitions ********************************************/
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/* Receive Buffer Register RBR, address 0x15001000 */
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#define UART_RBR_SHIFT (0) /* Bits 0-7 */
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#define UART_RBR_MASK (0xff << UART_RBR_SHIFT)
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/* Transmitter Holding Register THR, address 0x15001000 */
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#define UART_THR_SHIFT (0) /* Bits 0-7 */
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#define UART_THR_MASK (0xff << UART_THR_SHIFT)
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/* Divisor register Latch LSB DLL, address 0x15001000 */
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#define UART_DLL_SHIFT (0) /* Bits 0-7 */
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#define UART_DLL_MASK (0xff << UART_DLL_SHIFT)
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/* Divisor latch register MSB DLM, address 0x15001004 */
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#define UART_DLM_SHIFT (0) /* Bits 0-7 */
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#define UART_DLM_MASK (0xff << UART_DLM_SHIFT)
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/* Interrupt Enable Register IER, address 0x15001004 */
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#define UART_IER_CTSINTEN (1 << 7) /* Bit 7: Enable modem status interrupt on CTS transition */
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#define UART_IER_MSINTEN (1 << 3) /* Bit 3: Enable Modem Status interrupt */
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#define UART_IER_RLSINTEN (1 << 2) /* Bit 2: Receiver Line Status interrupt enable */
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#define UART_IER_THREINTEN (1 << 1) /* Bit 1: Transmitter Holding Register Empty interrupt enable */
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#define UART_IER_RDAINTEN (1 << 0) /* Bit 0: Receive Data Available interrupt enable */
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#define UART_IER_ALLINTS (0x1f)
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/* Interrupt Identification Register IIR, address 0x15001008 */
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#define UART_IIR_FIFOEN_SHIFT (6) /* Bits 6-7: Copies of FCR[0] */
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#define UART_IIR_FIFOEN_MASK (3 << UART_IIR_FIFOEN_SHIFT)
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#define UART_IIR_INTID_SHIFT (1) /* Bits 1-3: Interrupt identification */
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#define UART_IIR_INTID_MASK (7 << UART_IIR_INTID_SHIFT)
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# define UART_IIR_INTID_MS (0 << UART_IIR_INTID_SHIFT) /* Modem status */
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# define UART_IIR_INTID_THRE (1 << UART_IIR_INTID_SHIFT) /* Transmitter Holding Register empty */
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# define UART_IIR_INTID_RDA (2 << UART_IIR_INTID_SHIFT) /* Received Data Available */
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# define UART_IIR_INTID_RLS (3 << UART_IIR_INTID_SHIFT) /* Receiver Line Status */
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# define UART_IIR_INTID_TIMEOUT (6 << UART_IIR_INTID_SHIFT) /* Character time-out */
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#define UART_IIR_NOINT (1 << 0) /* Bit 0: Interrupt status, 1=no interrupt */
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/* FIFO Control Register FCR, address 0x15001008 */
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#define UART_FCR_RXTRIGLEVEL_SHIFT (6) /* Bits 6-7: 7:6 Receiver trigger level selection */
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#define UART_FCR_RXTRIGLEVEL_MASK (3 << UART_FCR_RXTRIGLEVEL_SHIFT)
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# define UART_FCR_RXTRIGLEVEL_1 (0 << UART_FCR_RXTRIGLEVEL_SHIFT) /* Rx trigger at character 1 */
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# define UART_FCR_RXTRIGLEVEL_16 (1 << UART_FCR_RXTRIGLEVEL_SHIFT) /* Rx trigger at character 16 */
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# define UART_FCR_RXTRIGLEVEL_32 (2 << UART_FCR_RXTRIGLEVEL_SHIFT) /* Rx trigger at character 32 */
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# define UART_FCR_RXTRIGLEVEL_56 (3 << UART_FCR_RXTRIGLEVEL_SHIFT) /* Rx trigger at character 56 */
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#define UART_FCR_DMAMODE (1 << 3) /* Bit 3: DMA mode select */
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#define UART_FCR_TXFIFORST (1 << 2) /* Bit 2: Transmitter FIFO reset */
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#define UART_FCR_RXFIFORST (1 << 1) /* Bit 1: Receiver FIFO reset */
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#define UART_FCR_FIFOENABLE (1 << 0) /* Bit 0: Transmit and receive FIFO enable */
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/* Line Control Register LCR, address 0x1500100c */
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#define UART_LCR_DLAB (1 << 7) /* Bit 7: Divisor Latch Access bit */
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#define UART_LCR_BRKCTRL (1 << 6) /* Bit 6: Break control bit */
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#define UART_LCR_PARSTICK (1 << 5) /* Bit 5: Enable sticky parity mode */
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#define UART_LCR_PAREVEN (1 << 4) /* Bit 4: Select even parity */
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#define UART_LCR_PAREN (1 << 3) /* Bit 3: Parity enable */
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#define UART_LCR_NSTOPBITS (1 << 2) /* Bit 2: Number of stop bits selector */
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#define UART_LCR_WDLENSEL_SHIFT (0) /* Bits 0-1: Word length selector */
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#define UART_LCR_WDLENSEL_MASK (3 << UART_LCR_WDLENSEL_SHIFT)
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# define UART_LCR_WDLENSEL_5BITS (0 << UART_LCR_WDLENSEL_SHIFT) /* Char length=5 stopbits=1 or 1.5*/
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# define UART_LCR_WDLENSEL_6BITS (1 << UART_LCR_WDLENSEL_SHIFT) /* Char length=6 stopbits=1 or 2 */
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# define UART_LCR_WDLENSEL_7BITS (2 << UART_LCR_WDLENSEL_SHIFT) /* Char length=7 stopbits=1 or 2 */
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# define UART_LCR_WDLENSEL_8BITS (3 << UART_LCR_WDLENSEL_SHIFT) /* Char length=8 stopbits=1 or 2 */
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/* Modem Control Register MCR, address 0x15001010 */
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#define UART_MCR_AUTOCTSEN (1 << 7) /* Bit 7: Auto-cts flow control enable */
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#define UART_MCR_AUTORTSEN (1 << 6) /* Bit 6: Auto-rts flow control enable */
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#define UART_MCR_LOOPEN (1 << 4) /* Bit 4: Loop-back mode enable */
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#define UART_MCR_RTS (1 << 1) /* Bit 1: Request To Send */
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/* Line Status Register LSR, address 0x15001014 */
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#define UART_LSR_RXER (1 << 7) /* Bit 7: Error in receiver FIFO */
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#define UART_LSR_TEMT (1 << 6) /* Bit 6: Transmitter empty (TSR and THR) */
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#define UART_LSR_THRE (1 << 5) /* Bit 5: Transmitter Holding Register empty */
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#define UART_LSR_BI (1 << 4) /* Bit 4: Break indication */
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#define UART_LSR_FE (1 << 3) /* Bit 3: Framing error */
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#define UART_LSR_PE (1 << 2) /* Bit 2: Parity error */
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#define UART_LSR_OE (1 << 1) /* Bit 1: Overrun error */
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#define UART_LSR_RDR (1 << 0) /* Bit 0: Read Data ready */
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/* Modem Status Register MSR, address 0x15001018 */
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#define UART_MSR_CTS (1 << 4) /* Bit 4: CTS is modem flow control signal */
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#define UART_MSR_DCTS (1 << 0) /* Bit 0: Delta Clear To Send */
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/* Scratch Register SCR, address 0x1500101c */
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#define UART_SCR_SCRVAL_SHIFT (0) /* Bits 0-7: Scratch Value */
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#define UART_SCR_SCRVAL_MASK (0xff << bb)
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/* IrDA Control Register ICR, address 0x15001024 */
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#define UART_ICR_PULSEDIV_SHIFT (3) /* Bits 3-5: Configures fixed pulse width mode */
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#define UART_ICR_PULSEDIV_MASK (7 << UART_ICR_PULSEDIV_SHIFT)
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#define UART_ICR_FIXPULSEEN (1 << 2) /* Bit 2: Enables IrDA fixed pulse width mode */
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#define UART_ICR_IRDAINV (1 << 1) /* Bit 1: Serial input is inverted */
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#define UART_ICR_IRDAEN (1 << 0) /* Bit 0: Enable IrDA */
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/* Fractional Divider Register FDR, address 0x15001028 */
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#define UART_FDR_MULVAL_SHIFT (4) /* Bits 4-7: Baud pre-scaler multiplier value */
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#define UART_FDR_MULVAL_MASK (15 << UART_FDR_MULVAL_SHIFT)
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#define UART_FDR_DIVADDVAL_SHIFT (0) /* Bits 0-3: Baud pre-scaler divisor value */
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#define UART_FDR_DIVADDVAL_MASK (15 << UART_FDR_DIVADDVAL_SHIFT)
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/* NHP POP Register POP, address 0x15001030 */
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#define UART_POP_POPRBR (1 << 0) /* Bit 0: Pop from RBR as if RBR read in non-NHP mode */
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/* Mode Selection Register MODE, 0x15001034 */
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#define UART_MODE_NHP (1 << 0) /* Bit 0: Enable UART NHP mode */
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/* Interrupt Clear Enable Register INTCE, address 0x15001fd8
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* Interrupt Set Enable Register INTSE, address 0x15001fdc
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* Interrupt Status Register INTS, address 0x15001fe0
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* Interrupt Enable Register INTE, address 0x15001fe4
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* Interrupt Clear Status Register INTCS, address 0x15001fe8
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* Interrupt Set Status Register INTSS, address 0x15001fec
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*/
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#define UART_OEINT (1 << 15) /* Bit 15: Overrun Error Interrupt */
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#define UART_PEINT (1 << 14) /* Bit 14: Parity Error Interrupt (not INTSS) */
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#define UART_FEINT (1 << 13) /* Bit 13: Frame Error Interrupt (not INTSS) */
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#define UART_BIINT (1 << 12) /* Bit 12: Break Indication Interrupt (not INTSS) */
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#define UART_ABTOINT (1 << 9) /* Bit 9: Auto-Baud Time-Out Interrupt */
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#define UART_ABEOINT (1 << 8) /* Bit 8: End of Auto-Baud Interrupt */
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#define UART_RXDAINT (1 << 6) /* Bit 6: Receiver Data Available Interrupt (not INTSS) */
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#define UART_RXTOINT (1 << 5) /* Bit 5: Receiver Time-Out Interrupt (not INTCE) */
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#define UART_THREINT (1 << 4) /* Bit 4: Transmitter Holding Register Empty Interrupt */
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#define UART_DCTSINT (1 << 0) /* Bit 0: Delta Clear To Send Interrupt */
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/****************************************************************************
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* Public Types
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****************************************************************************/
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Public Functions Prototypes
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****************************************************************************/
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#endif /* __ARCH_ARM_SRC_LPC31XX_LPC31_UART_H */
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