54e630e14d
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
273 lines
8.1 KiB
C
273 lines
8.1 KiB
C
/****************************************************************************
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* arch/arm/src/lpc54xx/lpc54_start.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <assert.h>
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#include <debug.h>
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#include <nuttx/init.h>
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#include <arch/board/board.h>
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#include <arch/irq.h>
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#include "arm_internal.h"
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#include "nvic.h"
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#include "hardware/lpc54_syscon.h"
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#include "lpc54_clockconfig.h"
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#include "lpc54_userspace.h"
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#include "lpc54_lowputc.h"
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#include "lpc54_serial.h"
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#include "lpc54_start.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/****************************************************************************
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* Name: showprogress
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*
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* Description:
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* Print a character on the UART to show boot status.
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*
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****************************************************************************/
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#ifdef CONFIG_DEBUG_FEATURES
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# define showprogress(c) arm_lowputc(c)
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#else
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# define showprogress(c)
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#endif
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/* This describes the initial PLL configuration */
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static const struct pll_setup_s g_initial_pll_setup =
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{
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.pllclksel = BOARD_PLL_CLKSEL,
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.pllctrl = SYSCON_SYSPLLCTRL_SELR(BOARD_PLL_SELR) |
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SYSCON_SYSPLLCTRL_SELI(BOARD_PLL_SELI) |
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SYSCON_SYSPLLCTRL_SELP(BOARD_PLL_SELP),
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.pllmdec = (SYSCON_SYSPLLMDEC_MDEC(BOARD_PLL_MDEC)),
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.pllndec = (SYSCON_SYSPLLNDEC_NDEC(BOARD_PLL_NDEC)),
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.pllpdec = (SYSCON_SYSPLLPDEC_PDEC(BOARD_PLL_PDEC)),
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.pllfout = BOARD_PLL_FOUT,
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.pllflags = PLL_SETUPFLAG_WAITLOCK | PLL_SETUPFLAG_POWERUP,
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.ahbdiv = SYSCON_AHBCLKDIV_DIV(BOARD_AHBCLKDIV)
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};
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: lpc54_fpuconfig
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*
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* Description:
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* Configure the FPU. Relative bit settings:
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*
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* CPACR: Enables access to CP10 and CP11
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* CONTROL.FPCA: Determines whether the FP extension is active in the
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* current context:
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* FPCCR.ASPEN: Enables automatic FP state preservation, then the
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* processor sets this bit to 1 on successful completion of any FP
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* instruction.
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* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
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* done, the processor reserves space on the stack for the FP state,
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* but does not save that state information to the stack.
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*
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* Software must not change the value of the ASPEN bit or LSPEN bit while
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* either:
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* - the CPACR permits access to CP10 and CP11, that give access to the FP
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* extension, or
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* - the CONTROL.FPCA bit is set to 1
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*
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****************************************************************************/
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#ifdef CONFIG_ARCH_FPU
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#ifndef CONFIG_ARMV7M_LAZYFPU
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static inline void lpc54_fpuconfig(void)
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{
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uint32_t regval;
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/* Set CONTROL.FPCA so that we always get the extended context frame
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* with the volatile FP registers stacked above the basic context.
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*/
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regval = getcontrol();
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regval |= CONTROL_FPCA;
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setcontrol(regval);
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/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
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* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
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* are going to turn on CONTROL.FPCA for all contexts.
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*/
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regval = getreg32(NVIC_FPCCR);
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regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
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putreg32(regval, NVIC_FPCCR);
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/* Enable full access to CP10 and CP11 */
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regval = getreg32(NVIC_CPACR);
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regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
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putreg32(regval, NVIC_CPACR);
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}
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#else
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static inline void lpc54_fpuconfig(void)
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{
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uint32_t regval;
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/* Clear CONTROL.FPCA so that we do not get the extended context frame
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* with the volatile FP registers stacked in the saved context.
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*/
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regval = getcontrol();
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regval &= ~CONTROL_FPCA;
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setcontrol(regval);
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/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
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* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
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* are going to keep CONTROL.FPCA off for all contexts.
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*/
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regval = getreg32(NVIC_FPCCR);
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regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
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putreg32(regval, NVIC_FPCCR);
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/* Enable full access to CP10 and CP11 */
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regval = getreg32(NVIC_CPACR);
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regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
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putreg32(regval, NVIC_CPACR);
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}
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#endif
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#else
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# define lpc54_fpuconfig()
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#endif
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: _start
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*
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* Description:
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* This is the reset entry point.
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*
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****************************************************************************/
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void __start(void)
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{
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const uint32_t *src;
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uint32_t *dest;
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uint32_t regval;
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/* Make sure that interrupts are disabled */
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__asm__ __volatile__ ("\tcpsid i\n");
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/* Enable the SRAM clock to make the stack usable */
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regval = (SYSCON_AHBCLKCTRL0_SRAM1 | SYSCON_AHBCLKCTRL0_SRAM2 |
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SYSCON_AHBCLKCTRL0_SRAM3);
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putreg32(regval, LPC54_SYSCON_AHBCLKCTRLSET0);
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/* Configure the clocking and the console uart so that we can get debug
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* output as soon as possible. NOTE: That this logic must not assume that
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* .bss or .data have beeninitialized.
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*/
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lpc54_clockconfig(&g_initial_pll_setup);
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lpc54_lowsetup();
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showprogress('A');
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/* Clear .bss. We'll do this inline (vs. calling memset) just to be
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* certain that there are no issues with the state of global variables.
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*/
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for (dest = &_sbss; dest < &_ebss; )
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{
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*dest++ = 0;
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}
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showprogress('B');
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/* Move the initialized data section from his temporary holding spot in
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* FLASH into the correct place in SRAM. The correct place in SRAM is
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* give by _sdata and _edata. The temporary location is in FLASH at the
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* end of all of the other read-only data (.text, .rodata) at _eronly.
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*/
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for (src = &_eronly, dest = &_sdata; dest < &_edata; )
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{
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*dest++ = *src++;
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}
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showprogress('C');
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/* Initialize the FPU (if configured) */
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lpc54_fpuconfig();
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showprogress('D');
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/* Perform early serial initialization */
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#ifdef USE_EARLYSERIALINIT
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lpc54_earlyserialinit();
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#endif
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showprogress('E');
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/* For the case of the separate user-/kernel-space build, perform whatever
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* platform specific initialization of the user memory is required.
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* Normally this just means initializing the user space .data and .bss
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* segments.
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*/
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#ifdef CONFIG_BUILD_PROTECTED
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lpc54_userspace();
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showprogress('F');
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#endif
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/* Initialize onboard resources */
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lpc54_board_initialize();
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showprogress('G');
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/* Then start NuttX */
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showprogress('\r');
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showprogress('\n');
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nx_start();
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/* Shouldn't get here */
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for (; ; );
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}
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