e54fe68bbf
This patch adds new chip family, stm32wl5x. This is bare minimum
implementation of said chip. I've tested this by running nsh.
There are only two chips in this family, stm32wl55 and stm32wl54.
The only difference between them is that stm32wl55 has LORA.
stm32wl5 is dual CPU (not core!). Right now only CPU1 is implemented.
CPU0 has access to radio hardware (while CPU1 does not). Chip is
designed so that CPU0 handles radio traffic while CPU1 does the
heavy lifting with data - there is communication pipe between two
CPUs.
I plan to use nuttx on CPU1 and LORA from stm32cube on CPU0 so I
don't have implementing CPU0 right now - once we have working LORA
in nuttx this may change.
Peripherals (except for radio) are shared so it's best to focus on
CPU1 to initialize all peripherals so that CPU0 can only use them
later. There is no real benefit to implement CPU0 if we don't have
working LORA/radio support in nuttx.
In time I will be implementing more and more things from this chip.
Right now I would like this minimal implementation to be merged in
case someone wants to work on this chip as well.
Signed-off-by: Michał Łyszczek <michal.lyszczek@bofc.pl>
---
patch v1->v2
- fixed formatting (suggested by Alan Carvalho de Assis)
- rebased patch to master (previous patch was based on nuttx-10.2
and did not compile on master)
150 lines
4.9 KiB
C
150 lines
4.9 KiB
C
/****************************************************************************
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* arch/arm/src/stm32wl5/stm32wl5_timerisr.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <time.h>
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#include <debug.h>
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#include <nuttx/arch.h>
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#include <arch/board/board.h>
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#include "nvic.h"
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#include "clock/clock.h"
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#include "arm_internal.h"
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#include "arm_internal.h"
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#include "chip.h"
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#include "stm32wl5.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* The desired timer interrupt frequency is provided by the definition
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* CLK_TCK (see include/time.h). CLK_TCK defines the desired number of
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* system clock ticks per second. That value is a user configurable setting
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* that defaults to 100 (100 ticks per second = 10 MS interval).
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*
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* The RCC feeds the Cortex System Timer (SysTick) with the AHB clock (HCLK)
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* divided by 8. The SysTick can work either with this clock or with the
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* Cortex clock (HCLK), configurable in the SysTick Control and Status
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* register.
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*/
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/* Power up default is HCLK, not HCLK/8.
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* And I don't know now to re-configure it yet
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*/
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#undef CONFIG_STM32WL5_SYSTICK_HCLKd8
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#ifdef CONFIG_STM32WL5_SYSTICK_HCLKd8
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# define SYSTICK_RELOAD ((STM32WL5_HCLK_FREQUENCY / 8 / CLK_TCK) - 1)
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#else
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# define SYSTICK_RELOAD ((STM32WL5_HCLK_FREQUENCY / CLK_TCK) - 1)
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#endif
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/* The size of the reload field is 24 bits. Verify that the reload value
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* will fit in the reload register.
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*/
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#if SYSTICK_RELOAD > 0x00ffffff
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# error SYSTICK_RELOAD exceeds the range of the RELOAD register
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#endif
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Function: stm32wl5_timerisr
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*
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* Description:
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* The timer ISR will perform a variety of services for various portions
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* of the systems.
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*
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****************************************************************************/
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static int stm32wl5_timerisr(int irq, uint32_t *regs, void *arg)
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{
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/* Process timer interrupt */
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nxsched_process_timer();
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return 0;
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Function: up_timer_initialize
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*
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* Description:
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* This function is called during start-up to initialize
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* the timer interrupt.
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*
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****************************************************************************/
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void up_timer_initialize(void)
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{
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uint32_t regval;
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/* Set the SysTick interrupt to the default priority */
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regval = getreg32(NVIC_SYSH12_15_PRIORITY);
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regval &= ~NVIC_SYSH_PRIORITY_PR15_MASK;
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regval |= (NVIC_SYSH_PRIORITY_DEFAULT << NVIC_SYSH_PRIORITY_PR15_SHIFT);
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putreg32(regval, NVIC_SYSH12_15_PRIORITY);
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/* Make sure that the SYSTICK clock source is set correctly */
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#if 0 /* Does not work. Comes up with HCLK source and I can't change it */
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regval = getreg32(NVIC_SYSTICK_CTRL);
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#ifdef CONFIG_STM32WL5_SYSTICK_HCLKd8
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regval &= ~NVIC_SYSTICK_CTRL_CLKSOURCE;
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#else
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regval |= NVIC_SYSTICK_CTRL_CLKSOURCE;
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#endif
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putreg32(regval, NVIC_SYSTICK_CTRL);
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#endif
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/* Configure SysTick to interrupt at the requested rate */
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putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD);
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/* Attach the timer interrupt vector */
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(void)irq_attach(STM32WL5_IRQ_SYSTICK, (xcpt_t)stm32wl5_timerisr, NULL);
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/* Enable SysTick interrupts */
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putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE | NVIC_SYSTICK_CTRL_TICKINT |
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NVIC_SYSTICK_CTRL_ENABLE), NVIC_SYSTICK_CTRL);
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/* And enable the timer interrupt */
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up_enable_irq(STM32WL5_IRQ_SYSTICK);
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}
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