lc823450 spif boot * arch/arm/src/lc823450: Add support for SPI flash boot Also, remove unnecessary code for the SPI flash boot Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com> * configs/lc823450-xgevk: Add linker script for SPI flash boot Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com> Approved-by: GregoryN <gnutt@nuttx.org>
418 lines
12 KiB
C
418 lines
12 KiB
C
/****************************************************************************
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* arch/arm/src/lc823450/lc823450_start.c
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*
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* Copyright 2014, 2015, 2016, 2017, 2018 Sony Video & Sound Products Inc.
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* Author: Masatoshi Tateishi <Masatoshi.Tateishi@jp.sony.com>
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* Author: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
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* Author: Yasuhiro Osaki <Yasuhiro.Osaki@jp.sony.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <assert.h>
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#include <debug.h>
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#include <string.h>
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#include <stdio.h>
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#include <nuttx/init.h>
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#include <nuttx/arch.h>
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#include <nuttx/mtd/mtd.h>
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#ifdef CONFIG_LASTKMSG
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# include <nuttx/lastkmsg.h>
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#endif /* CONFIG_LASTKMSG */
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#include "up_arch.h"
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#include "up_internal.h"
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#include "nvic.h"
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#include <arch/board/board.h>
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#ifdef CONFIG_LC823450_SPIFI
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# include "lc823450_spifi2.h"
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#endif
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#include "lc823450_lowputc.h"
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#include "lc823450_clockconfig.h"
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#include "lc823450_syscontrol.h"
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#ifdef CONFIG_BUILD_PROTECTED
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# include "lc823450_userspace.h"
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#endif
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#include "lc823450_gpio.h"
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#ifdef CONFIG_MM_MULTIHEAP
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# include "lc823450_sram.h"
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#endif
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#ifdef CONFIG_LC823450_SDRAM
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# include "lc823450_sdram.h"
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#endif
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#include "lc823450_start.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* .data is positioned first in the primary RAM followed immediately by .bss.
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* The IDLE thread stack lies just after .bss and has size give by
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* CONFIG_IDLETHREAD_STACKSIZE; The heap then begins just after the IDLE.
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* ARM EABI requires 64 bit stack alignment.
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*/
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#define IDLE_STACKSIZE (CONFIG_IDLETHREAD_STACKSIZE & ~7)
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#define IDLE_STACK ((uintptr_t)&_ebss + IDLE_STACKSIZE)
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#define HEAP_BASE ((uintptr_t)&_ebss + IDLE_STACKSIZE)
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/* g_idle_topstack: _sbss is the start of the BSS region as defined by the
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* linker script. _ebss lies at the end of the BSS region. The idle task
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* stack starts at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE.
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* The IDLE thread is the thread that the system boots on and, eventually,
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* becomes the IDLE, do nothing task that runs only when there is nothing
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* else to run. The heap continues from there until the end of memory.
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* g_idle_topstack is a read-only variable the provides this computed
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* address.
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*/
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const uintptr_t g_idle_topstack = HEAP_BASE;
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/****************************************************************************
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* Public Data
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****************************************************************************/
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int icx_boot_reason;
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extern uint32_t _stext_sram, _etext_sram, _ftext, _svect;
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/****************************************************************************
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* Private Function prototypes
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****************************************************************************/
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#ifdef CONFIG_STACK_COLORATION
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static void go_os_start(void *pv, unsigned int nbytes)
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__attribute__ ((naked, no_instrument_function, noreturn));
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#endif
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: showprogress
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*
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* Description:
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* Print a character on the UART to show boot status.
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*
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****************************************************************************/
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#ifdef CONFIG_DEBUG_FEATURES
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# define showprogress(c) up_lowputc(c)
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#else
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# define showprogress(c)
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#endif
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/****************************************************************************
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* Name: go_os_start
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*
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* Description:
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* Set the IDLE stack to the coloration value and jump into os_start()
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*
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****************************************************************************/
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#ifdef CONFIG_STACK_COLORATION
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static void go_os_start(void *pv, unsigned int nbytes)
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{
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/* Set the IDLE stack to the stack coloration value then jump to
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* os_start(). We take extreme care here because were currently
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* executing on this stack.
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*
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* We want to avoid sneak stack access generated by the compiler.
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*/
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__asm__ __volatile__
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(
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"\tmov r1, r1, lsr #2\n" /* R1 = nwords = nbytes >> 2 */
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"\tcmp r1, #0\n" /* Check (nwords == 0) */
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"\tbeq 2f\n" /* (should not happen) */
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"\tbic r0, r0, #3\n" /* R0 = Aligned stackptr */
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"\tmovw r2, #0xbeef\n" /* R2 = STACK_COLOR = 0xdeadbeef */
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"\tmovt r2, #0xdead\n"
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"1:\n" /* Top of the loop */
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"\tsub r1, r1, #1\n" /* R1 nwords-- */
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"\tcmp r1, #0\n" /* Check (nwords == 0) */
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"\tstr r2, [r0], #4\n" /* Save stack color word, increment stackptr */
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"\tbne 1b\n" /* Bottom of the loop */
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"2:\n"
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"\tmov r14, #0\n" /* LR = return address (none) */
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"\tb os_start\n" /* Branch to os_start */
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);
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}
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#endif
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: _start
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*
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* Description:
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* This is the reset entry point.
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*
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****************************************************************************/
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void __start(void)
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{
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const uint32_t *src;
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uint32_t *dest;
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/* Clear .bss. We'll do this inline (vs. calling memset) just to be
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* certain that there are no issues with the state of global variables.
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*/
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#ifdef CONFIG_FS_EVFAT
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/* clear the work area in seg0 */
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dest = (uint32_t *)0x02000000;
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int i;
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for (i = 0; i < 0xe00 / sizeof(uint32_t); i++)
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{
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*dest++ = 0;
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}
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#endif
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for (dest = &_sbss; dest < &_ebss; )
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{
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*dest++ = 0;
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}
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/* Move the initialized data section from his temporary holding spot in
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* FLASH into the correct place in SRAM. The correct place in SRAM is
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* give by _sdata and _edata. The temporary location is in FLASH at the
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* end of all of the other read-only data (.text, .rodata) at _eronly.
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*/
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for (src = &_eronly, dest = &_sdata; dest < &_edata; )
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{
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*dest++ = *src++;
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}
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/* run as interrupt context, before scheduler running */
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CURRENT_REGS = (uint32_t *)1;
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#ifdef CONFIG_LASTKMSG_LOWOUTS
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if (g_lastksg_buf.sig == LASTKMSG_SIG_REBOOT)
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{
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icx_boot_reason |= ICX_BOOT_REASON_REBOOT;
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}
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/* clrear kmsg buffer */
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memset(&g_lastksg_buf, 0, sizeof(g_lastksg_buf));
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/* set lastkmsg signature */
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g_lastksg_buf.sig = LASTKMSG_SIG;
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#endif /* CONFIG_LASTKMSG */
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#ifdef CONFIG_LC823450_SPIFI_BOOT
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/* Copy any necessary code sections from FLASH to RAM. The correct
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* destination in SRAM is geive by _sramfuncs and _eramfuncs. The
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* temporary location is in flash after the data initialization code
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* at _framfuncs. This should be done before lc823450_clockconfig() is
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* called (in case it has some dependency on initialized C variables).
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*/
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#ifdef CONFIG_ARCH_RAMFUNCS
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for (src = &_framfuncs, dest = &_sramfuncs; dest < &_eramfuncs; )
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{
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*dest++ = *src++;
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}
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#endif
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#else /* CONFIG_LC823450_SPIFI_BOOT */
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/* vector offset */
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#ifdef CONFIG_LC823450_IPL2
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putreg32(0x02000e00, 0xe000ed08);
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putreg32(0x0, 0x40080008); /* XXX: remap disable */
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#else /* CONFIG_LC823450_IPL2 */
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putreg32(0x02040000, 0xe000ed08);
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#endif /* CONFIG_LC823450_IPL2 */
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#endif /* CONFIG_LC823450_SPIFI_BOOT */
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/* Enable Mutex */
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/* NOTE: modyfyreg32() can not be used because it might use spin_lock */
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uint32_t val = getreg32(MRSTCNTBASIC);
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val |= MRSTCNTBASIC_MUTEX_RSTB;
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putreg32(val, MRSTCNTBASIC);
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/* Configure the uart so that we can get debug output as soon as possible */
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lc823450_clockconfig();
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lc823450_lowsetup();
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showprogress('A');
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/* IPL2 don't change mux */
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#ifdef CONFIG_LC823450_IPL2
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/* GPIO2F out High in IPL2 */
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modifyreg32(MCLKCNTAPB, 0, MCLKCNTAPB_PORT2_CLKEN);
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modifyreg32(MRSTCNTAPB, 0, MRSTCNTAPB_PORT2_RSTB);
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modifyreg32(rP2DT, 0, 1 << 15 /* GPIO2F */);
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modifyreg32(rP2DRC, 0, 1 << 15 /* GPIO2F */);
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#ifdef CONFIG_DEBUG_FEATURES
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/* enable TXD0 for debug */
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modifyreg32(PMDCNT5, 0, 3 << 14);
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#endif /* CONFIG_DEBUG_FEATURES */
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#else /* CONFIG_LC823450_IPL2 */
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up_init_default_mux();
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#endif /* CONFIG_LC823450_IPL2 */
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showprogress('B');
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#if defined(CONFIG_LC823450_SPIFI) && !defined(CONFIG_LC823450_SPIFI_BOOT)
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lc823450_spiflash_earlyinit();
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#endif /* CONFIG_LC823450_SPIFI */
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#ifdef CONFIG_LC823450_SDRAM
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lc823450_sdram_init();
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#endif /* CONFIG_LC823450_SDRAM */
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showprogress('C');
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/* Perform early serial initialization */
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#ifdef USE_EARLYSERIALINIT
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up_earlyserialinit();
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#endif
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showprogress('D');
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/* For the case of the separate user-/kernel-space build, perform whatever
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* platform specific initialization of the user memory is required.
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* Normally this just means initializing the user space .data and .bss
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* segments.
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*/
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#ifdef CONFIG_BUILD_PROTECTED
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lc823450_userspace();
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#endif
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#if defined(CONFIG_BUILD_FLAT) && defined(CONFIG_ARM_MPU)
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lc823450_mpuinitialize();
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#endif
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showprogress('E');
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#ifdef CONFIG_MM_MULTIHEAP
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lc823450_sram_initialize();
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#endif
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showprogress('F');
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#ifndef CONFIG_LC823450_IPL2
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sinfo("icx_boot_reason = 0x%x\n", icx_boot_reason);
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#endif /* CONFIG_LC823450_IPL2 */
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#ifdef CONFIG_POWERBUTTON_LDOWN
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if (icx_boot_reason & ICX_BOOT_REASON_POWERBUTTON)
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{
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int t = 1000;
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while (--t && up_board_powerkey())
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{
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up_udelay(10 * 1000);
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}
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sinfo("t = %d\n", t);
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if (t)
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{
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up_board_poweren(0);
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up_udelay(1000 * 1000);
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sinfo("VBUS connected ?\n");
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/* VBUS is connected after powerup by key.
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* Resume PowerOn sequence. (cancel shutdown)
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*/
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up_board_poweren(1);
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}
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}
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#endif /* CONFIG_POWERBUTTON_LDOWN */
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/* Then start NuttX */
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showprogress('\r');
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showprogress('\n');
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(void)get_cpu_ver();
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/* run as interrupt context, before scheduler running */
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CURRENT_REGS = NULL;
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#ifdef CONFIG_STACK_COLORATION
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/* Set the IDLE stack to the coloration value and jump into os_start() */
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go_os_start((FAR void *)&_ebss, CONFIG_IDLETHREAD_STACKSIZE);
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#else
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/* Call os_start() */
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os_start();
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/* Shoulnd't get here */
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for (;;);
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#endif
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}
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