116 lines
4.3 KiB
ArmAsm
116 lines
4.3 KiB
ArmAsm
/****************************************************************************
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* arch/arm/src/armv7-a/cp15_flush_dcache.S
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*
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* References:
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*
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* "Cortex-A5™ MPCore, Technical Reference Manual", Revision: r0p1,
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* Copyright © 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810)
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* "ARM® Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
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* Copyright © 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM
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* DDI 0406C.b (ID072512)
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*
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* Portions of this file derive from Atmel sample code for the SAMA5D3 Cortex-A5
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* which also has a modified BSD-style license:
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*
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* Copyright (c) 2012, Atmel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor Atmel nor the names of the contributors may
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* be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include "cp15.h"
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.file "cp15_flush_dcache.S"
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/****************************************************************************
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* Preprocessor Definitions
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****************************************************************************/
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/****************************************************************************
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* Public Symbols
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****************************************************************************/
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.globl cp15_flush_dcache
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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.text
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/****************************************************************************
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* Name: cp15_flush_dcache
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*
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* Description:
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* Flush the data cache within the specified region by cleaning and
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* invalidating the D cache.
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*
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* Input Parameters:
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* start - virtual start address of region
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* end - virtual end address of region + 1
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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.globl cp15_flush_dcache
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.type cp15_flush_dcache, function
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cp15_flush_dcache:
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mrc CP15_TR(r3) /* Read the Cache Type Register */
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lsr r3, r3, #16 /* Isolate the DMinLine field */
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and r3, r3, #0xf
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mov r2, #4
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mov r2, r2, lsl r3 /* Get the cache line size in bytes */
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sub r3, r2, #1 /* R3=Cache line size mask */
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bic r0, r0, r3 /* R0=aligned start address */
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/* Loop, cleaning and invaliding each D cache line in the address range */
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1:
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mcrne CP15_DCCIMVAC(r0) /* Clean and invalidate data cache line by VA to PoC */
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add r0, r0, r2 /* R12=Next cache line */
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cmp r0, r1 /* Loop until all cache lines have been cleaned */
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blo 1b
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dsb
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bx lr
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.size cp15_flush_dcache, . - cp15_flush_dcache
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.end
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