230 lines
7.8 KiB
C
230 lines
7.8 KiB
C
/****************************************************************************
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* arch/arm/src/lpc17xx_40xx/lpc176x_clockconfig.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <debug.h>
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#include <nuttx/arch.h>
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#include <arch/board/board.h>
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#include "arm_internal.h"
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#include "lpc17_40_clockconfig.h"
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#include "hardware/lpc17_40_syscon.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#ifndef LPC176x
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# error "The logic in this file applies only to the LPC176x family"
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#endif
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: lpc17_40_clockconfig
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*
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* Description:
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* Called to initialize the LPC176x. This does whatever setup is needed to
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* put the SoC in a usable state. This includes the initialization of
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* clocking using the settings in board.h.
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*
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* The LPC176x and LPC178x/40xx system control block is *nearly* identical
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* but we have found that the LPC178x/40xx is more sensitive to the
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* ordering of certain operations. So, although the hardware seems very
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* similar, the safer thing to do is to separate the LPC176x and
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* LPC178x/40xx into separate files.
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*
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****************************************************************************/
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void lpc17_40_clockconfig(void)
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{
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/* Enable the main oscillator (or not) and
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* the frequency range of the main oscillator
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*/
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putreg32(BOARD_SCS_VALUE, LPC17_40_SYSCON_SCS);
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/* Wait for the main oscillator to be ready. */
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#ifdef CONFIG_LPC17_40_MAINOSC
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while ((getreg32(LPC17_40_SYSCON_SCS) & SYSCON_SCS_OSCSTAT) == 0);
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#endif
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/* Setup up the divider value for the CPU clock.
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* The output of the divider is CCLK.
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* The input to the divider (PLLCLK) is equal to SYSCLK unless PLL0 is
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* enabled. CCLK will be further divided to produce peripheral clocks,
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* but that peripheral clock setup is performed in the peripheral device
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* drivers. Here only CCLK is configured.
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*/
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putreg32(BOARD_CCLKCFG_VALUE, LPC17_40_SYSCON_CCLKCFG);
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/* PLL0 is used to generate the CPU clock divider input (PLLCLK). */
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#ifdef CONFIG_LPC17_40_PLL0
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/* Select the PLL0 source clock, multiplier, and pre-divider values.
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* NOTE that a special "feed" sequence must be written to the PLL0FEED
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* register in order for changes to the PLL0CFG register to take effect.
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*/
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putreg32(BOARD_CLKSRCSEL_VALUE, LPC17_40_SYSCON_CLKSRCSEL);
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putreg32(BOARD_PLL0CFG_VALUE, LPC17_40_SYSCON_PLL0CFG);
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putreg32(0xaa, LPC17_40_SYSCON_PLL0FEED);
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putreg32(0x55, LPC17_40_SYSCON_PLL0FEED);
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/* Enable the PLL.
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* NOTE that a special "feed" sequence must be written to the PLL0FEED
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* register in order for changes to the PLL0CON register to take effect.
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*/
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putreg32(SYSCON_PLLCON_PLLE, LPC17_40_SYSCON_PLL0CON);
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putreg32(0xaa, LPC17_40_SYSCON_PLL0FEED);
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putreg32(0x55, LPC17_40_SYSCON_PLL0FEED);
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/* Wait for PLL0 to lock */
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while ((getreg32(LPC17_40_SYSCON_PLL0STAT) & SYSCON_PLL0STAT_PLOCK) == 0);
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/* Enable and connect PLL0 */
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putreg32(SYSCON_PLLCON_PLLE | SYSCON_PLLCON_PLLC, LPC17_40_SYSCON_PLL0CON);
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putreg32(0xaa, LPC17_40_SYSCON_PLL0FEED);
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putreg32(0x55, LPC17_40_SYSCON_PLL0FEED);
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/* Wait for PLL to report that it is connected and enabled */
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while ((getreg32(LPC17_40_SYSCON_PLL0STAT) &
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(SYSCON_PLL0STAT_PLLE | SYSCON_PLL0STAT_PLLC))
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!= (SYSCON_PLL0STAT_PLLE | SYSCON_PLL0STAT_PLLC));
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#endif /* CONFIG_LPC17_40_PLL0 */
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/* PLL1 receives its clock input from the main oscillator only and can be
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* used to provide a fixed 48 MHz clock only to the USB subsystem
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* (if that clock cannot be obtained from PLL0).
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*/
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#ifdef CONFIG_LPC17_40_PLL1
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/* Select the PLL1 multiplier, and pre-divider values.
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* NOTE that a special "feed" sequence must be written to the PLL1FEED
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* register in order for changes to the PLL1CFG register to take effect.
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*/
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putreg32(BOARD_PLL1CFG_VALUE, LPC17_40_SYSCON_PLL1CFG);
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putreg32(0xaa, LPC17_40_SYSCON_PLL1FEED);
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putreg32(0x55, LPC17_40_SYSCON_PLL1FEED);
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/* Enable the PLL.
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* NOTE that a special "feed" sequence must be written to the PLL1FEED
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* register in order for changes to the PLL1CON register to take effect.
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*/
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putreg32(SYSCON_PLLCON_PLLE, LPC17_40_SYSCON_PLL1CON);
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putreg32(0xaa, LPC17_40_SYSCON_PLL1FEED);
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putreg32(0x55, LPC17_40_SYSCON_PLL1FEED);
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/* Wait for PLL1 to lock */
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while ((getreg32(LPC17_40_SYSCON_PLL1STAT) & SYSCON_PLL1STAT_PLOCK) == 0);
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/* Enable and connect PLL1 */
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putreg32(SYSCON_PLLCON_PLLE | SYSCON_PLLCON_PLLC, LPC17_40_SYSCON_PLL1CON);
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putreg32(0xaa, LPC17_40_SYSCON_PLL1FEED);
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putreg32(0x55, LPC17_40_SYSCON_PLL1FEED);
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/* Wait for PLL to report that it is connected and enabled */
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while ((getreg32(LPC17_40_SYSCON_PLL1STAT) &
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(SYSCON_PLL1STAT_PLLE | SYSCON_PLL1STAT_PLLC))
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!= (SYSCON_PLL1STAT_PLLE | SYSCON_PLL1STAT_PLLC));
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#else /* CONFIG_LPC17_40_PLL1 */
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/* Otherwise, setup up the USB clock divider to generate the USB clock
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* from PLL0
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*/
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putreg32(BOARD_USBCLKCFG_VALUE, LPC17_40_SYSCON_USBCLKCFG);
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#endif /* CONFIG_LPC17_40_PLL1 */
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/* Disable all peripheral clocks. They must be configured by each device
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* driver when the device driver is initialized.
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*/
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putreg32(0, LPC17_40_SYSCON_PCLKSEL0);
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putreg32(0, LPC17_40_SYSCON_PCLKSEL1);
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/* Disable power to all peripherals (execpt GPIO). Peripherals must be
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* re-powered one at a time by each device driver when the driver is
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* initialized.
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*/
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putreg32(SYSCON_PCONP_PCGPIO, LPC17_40_SYSCON_PCONP);
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/* Disable CLKOUT */
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putreg32(0, LPC17_40_SYSCON_CLKOUTCFG);
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/* Configure FLASH */
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#ifdef CONFIG_LPC17_40_FLASH
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{
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uint32_t regval;
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if (BOARD_FLASHCFG_VALUE & ~SYSCON_FLASHCFG_TIM_MASK)
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{
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regval = BOARD_FLASHCFG_VALUE;
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}
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else
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{
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regval = getreg32(LPC17_40_SYSCON_FLASHCFG);
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regval &= ~SYSCON_FLASHCFG_TIM_MASK;
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regval |= BOARD_FLASHCFG_VALUE;
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}
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putreg32(regval, LPC17_40_SYSCON_FLASHCFG);
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}
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#endif
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}
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