727 lines
46 KiB
C
727 lines
46 KiB
C
/************************************************************************************
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* arch/arm/include/lpc43xx/chip.h
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*
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* Copyright (C) 2012-2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_LPC43XX_CHIP_H
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#define __ARCH_ARM_INCLUDE_LPC43XX_CHIP_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Per the data sheet: LPC4350/30/20/10 Rev. 3.2 — 4 June 2012 */
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/* Get customizations for each supported chip.
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*
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* SRAM Resources
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* --------------------- -------- ------- ------- -------
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* Local SRAM LPC4310 LPC4320 LPC4330 LPC4350
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* --------------------- -------- ------- ------- -------
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* BANK 0 (0x1000 0000) 96Kb 128Kb 128Kb 128Kb
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* BANK 1 (0x1008 0000) 40Kb 40Kb 72Kb 72Kb
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* --------------------- -------- ------- ------- -------
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* SUBTOTAL 136Kb 168Kb 200Kb 200Kb
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* --------------------- -------- ------- ------- -------
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* AHB SRAM LPC4310 LPC4320 LPC4330 LPC4350
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* --------------------- -------- ------- ------- -------
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* BANK 0 (0x2000 0000) 16Kb 48Kb 48Kb 48Kb
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* BANK 1 (0x2000 8000) NOTE 1 NOTE 1 NOTE 1
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* BANK 2 (0x2000 c000) 16Kb 16Kb 16Kb 16Kb
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* --------------------- -------- ------- ------- -------
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* SUBTOTAL 32Kb 32Kb 64Kb 64Kb
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* --------------------- -------- ------- ------- -------
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* TOTAL 168Kb 200Kb 264Kb 264Kb
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* --------------------- -------- ------- ------- -------
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*
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* NOTE 1: The 64Kb of AHB of SRAM on the LPC4350/30/20 span all AHB SRAM
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* banks but are treated as two banks of 48 an 16Kb by the NuttX memory
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* manager. This gives some symmetry to all of the members of the family.
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*/
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/* Per the user manual: UM10503, Rev. 1.2 — 8 June 2012 */
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/* Get customizations for each supported chip.
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*
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* SRAM Resources
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* --------------------- -------- ------- ------- ------- ------- ------- -------
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* Local SRAM LPC4310 LPC4320 LPC4330 LPC4350 LPC4353 LPC4357 LPC4337
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* --------------------- -------- ------- ------- ------- ------- ------- -------
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* BANK 0 (0x1000 0000) 96Kb 96Kb 128Kb 128Kb 32Kb 32Kb 32Kb
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* BANK 1 (0x1008 0000) 40Kb 40Kb 72Kb 72Kb 40Kb 40Kb 40Kb
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* --------------------- -------- ------- ------- ------- ------- ------- -------
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* SUBTOTAL 136Kb 136Kb 200Kb 200Kb 72Kb 72Kb 72Kb
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* --------------------- -------- ------- ------- ------- ------- ------- -------
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* AHB SRAM LPC4310 LPC4320 LPC4330 LPC4350 LPC4353 LPC4357 LPC4337
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* --------------------- -------- ------- ------- ------- ------- ------- -------
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* BANK 0 (0x2000 0000) 16Kb 48Kb 48Kb 48Kb 48Kb 48Kb 48Kb
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* BANK 1 (0x2000 8000) NOTE 1 NOTE 1 NOTE 1 NOTE 1 NOTE 1 NOTE 1
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* BANK 2 (0x2000 c000) 16Kb 16Kb 16Kb 16Kb 16Kb 16Kb 16Kb
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* --------------------- -------- ------- ------- ------- ------- ------- -------
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* SUBTOTAL 32Kb 64Kb 64Kb 64Kb 64Kb 64Kb 64Kb
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* --------------------- -------- ------- ------- ------- ------- ------- -------
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* TOTAL 168Kb 200Kb 264Kb 264Kb 136Kb 136Kb 136Kb
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* --------------------- -------- ------- ------- ------- ------- ------- -------
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*
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* --------------------- -------- ------- ------- ------- ------- ------- -------
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* FLASH LPC4310 LPC4320 LPC4330 LPC4350 LPC4353 LPC4357 LPC4337
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* --------------------- -------- ------- ------- ------- ------- ------- -------
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* BANK A (0x1a00 0000) 256Kb 512Kb 512Kb
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* BANK B (0x1b00 8000) 256Kb 512Kb 512Kb
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* --------------------- -------- ------- ------- ------- ------- ------- -------
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* TOTAL None None None None 512Kb 1024Kb 1024Kb
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* --------------------- -------- ------- ------- ------- ------- ------- -------
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*
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* NOTE 1: The 64Kb of AHB of SRAM on the LPC4350/30/20 span all AHB SRAM
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* banks but are treated as two banks of 48 an 16Kb by the NuttX memory
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* manager. This gives some symmetry to all of the members of the family.
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*/
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#if defined(CONFIG_ARCH_CHIP_LPC4310FBD144)
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# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
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# define LPC43_FLASH_BANKB_SIZE (0)
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# define LPC43_LOCSRAM_BANK0_SIZE (96*1024) /* 136Kb Local SRAM */
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# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
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# define LPC43_AHBSRAM_BANK0_SIZE (16*1024) /* 32Kb AHB SRAM */
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# define LPC43_AHBSRAM_BANK1_SIZE (0)
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# define LPC43_AHBSRAM_BANK2_SIZE (16*1024)
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# define LPC43_EEPROM_SIZE (0) /* No EEPROM */
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# undef LPC43_NLCD /* No LCD controller */
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# undef LPC43_ETHERNET /* No Ethernet controller */
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# undef LPC43_USB0 /* No USB0 (Host, Device, OTG) */
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# undef LPC43_USB1 /* No USB1 (Host, Device) */
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# undef LPC43_USB1_ULPI /* No USB1 (Host, Device) with ULPI I/F */
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# define LPC43_MCPWM (1) /* One PWM interface */
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# undef LPC43_QEI /* No Quadrature Encoder capability */
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# define LPC43_NUSARTS (4) /* Three USARTs + 1 UART */
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# define LPC43_NSSP (2) /* Two SSP controllers */
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# define LPC43_NTIMERS (4) /* Four Timers */
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# define LPC43_NI2C (2) /* Two I2C controllers */
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# define LPC43_NI2S (2) /* Two I2S controllers */
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# define LPC43_NCAN (2) /* Two CAN controllers */
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# define LPC43_NDAC (1) /* One 10-bit DAC */
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# define LPC43_NADC10 (2) /* Two 10-bit ADC controllers */
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# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
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# undef LPC43_NADC12 /* No 12-bit ADC controllers */
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#elif defined(CONFIG_ARCH_CHIP_LPC4310FET100)
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# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
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# define LPC43_FLASH_BANKB_SIZE (0)
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# define LPC43_LOCSRAM_BANK0_SIZE (96*1024) /* 136Kb Local SRAM */
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# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
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# define LPC43_AHBSRAM_BANK0_SIZE (16*1024) /* 32Kb AHB SRAM */
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# define LPC43_AHBSRAM_BANK1_SIZE (0)
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# define LPC43_AHBSRAM_BANK2_SIZE (16*1024)
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# define LPC43_EEPROM_SIZE (0) /* No EEPROM */
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# undef LPC43_NLCD /* No LCD controller */
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# undef LPC43_ETHERNET /* No Ethernet controller */
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# undef LPC43_USB0 /* No USB0 (Host, Device, OTG) */
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# undef LPC43_USB1 /* No USB1 (Host, Device) */
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# undef LPC43_USB1_ULPI /* No USB1 (Host, Device) with ULPI I/F */
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# undef LPC43_MCPWM /* No PWM capability */
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# undef LPC43_QEI /* No Quadrature Encoder capability */
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# define LPC43_NUSARTS (4) /* Three USARTs + 1 UART */
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# define LPC43_NSSP (2) /* Two SSP controllers */
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# define LPC43_NTIMERS (4) /* Four Timers */
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# define LPC43_NI2C (2) /* Two I2C controllers */
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# define LPC43_NI2S (2) /* Two I2S controllers */
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# define LPC43_NCAN (2) /* Two CAN controllers */
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# define LPC43_NDAC (1) /* One 10-bit DAC */
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# define LPC43_NADC10 (2) /* Two 10-bit ADC controllers */
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# define LPC43_NADC10_CHANNELS (4) /* Four ADC channels */
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# undef LPC43_NADC12 /* No 12-bit ADC controllers */
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#elif defined(CONFIG_ARCH_CHIP_LPC4320FBD144)
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# warning "Data sheet and user manual are consistement for the LPC4320"
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# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
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# define LPC43_FLASH_BANKB_SIZE (0)
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# define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 168Kb Local SRAM*/
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# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
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# define LPC43_AHBSRAM_BANK0_SIZE (16*1024) /* 32Kb AHB SRAM */
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# define LPC43_AHBSRAM_BANK1_SIZE (0)
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# define LPC43_AHBSRAM_BANK2_SIZE (16*1024)
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# define LPC43_EEPROM_SIZE (0) /* No EEPROM */
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# undef LPC43_NLCD /* No LCD controller */
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# undef LPC43_ETHERNET /* No Ethernet controller */
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# define LPC43_USB0 (1) /* Have USB0 (Host, Device, OTG) */
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# undef LPC43_USB1 /* No USB1 (Host, Device) */
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# undef LPC43_USB1_ULPI /* No USB1 (Host, Device) with ULPI I/F */
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# define LPC43_MCPWM (1) /* One PWM interface */
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# undef LPC43_QEI /* No Quadrature Encoder capability */
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# define LPC43_NUSARTS (4) /* Three USARTs + 1 UART */
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# define LPC43_NSSP (2) /* Two SSP controllers */
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# define LPC43_NTIMERS (4) /* Four Timers */
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# define LPC43_NI2C (2) /* Two I2C controllers */
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# define LPC43_NI2S (2) /* Two I2S controllers */
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# define LPC43_NCAN (2) /* Two CAN controllers */
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# define LPC43_NDAC (1) /* One 10-bit DAC */
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# define LPC43_NADC10 (2) /* Two 10-bit ADC controllers */
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# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
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# undef LPC43_NADC12 /* No 12-bit ADC controllers */
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#elif defined(CONFIG_ARCH_CHIP_LPC4320FET100)
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# warning "Data sheet and user manual are consistement for the LPC4320"
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# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
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# define LPC43_FLASH_BANKB_SIZE (0)
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# define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 168Kb Local SRAM*/
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# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
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# define LPC43_AHBSRAM_BANK0_SIZE (16*1024) /* 32Kb AHB SRAM */
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# define LPC43_AHBSRAM_BANK1_SIZE (0)
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# define LPC43_AHBSRAM_BANK2_SIZE (16*1024)
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# define LPC43_EEPROM_SIZE (0) /* No EEPROM */
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# undef LPC43_NLCD /* No LCD controller */
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# undef LPC43_ETHERNET /* No Ethernet controller */
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# define LPC43_USB0 (1) /* Have USB0 (Host, Device, OTG) */
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# undef LPC43_USB1 /* No USB1 (Host, Device) */
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# undef LPC43_USB1_ULPI /* No USB1 (Host, Device) with ULPI I/F */
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# undef LPC43_MCPWM /* No PWM capability */
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# undef LPC43_QEI /* No Quadrature Encoder capability */
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# define LPC43_NUSARTS (4) /* Three USARTs + 1 UART */
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# define LPC43_NSSP (2) /* Two SSP controllers */
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# define LPC43_NTIMERS (4) /* Four Timers */
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# define LPC43_NI2C (2) /* Two I2C controllers */
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# define LPC43_NI2S (2) /* Two I2S controllers */
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# define LPC43_NCAN (2) /* Two CAN controllers */
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# define LPC43_NDAC (1) /* One 10-bit DAC */
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# define LPC43_NADC10 (2) /* Two 10-bit ADC controllers */
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# define LPC43_NADC10_CHANNELS (4) /* Four ADC channels */
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# undef LPC43_NADC12 /* No 12-bit ADC controllers */
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#elif defined(CONFIG_ARCH_CHIP_LPC4330FBD144)
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# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
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# define LPC43_FLASH_BANKB_SIZE (0)
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# define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 200Kb Local SRAM*/
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# define LPC43_LOCSRAM_BANK1_SIZE (72*1024)
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# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
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# define LPC43_AHBSRAM_BANK1_SIZE (0)
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# define LPC43_AHBSRAM_BANK2_SIZE (16*1024)
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# define LPC43_EEPROM_SIZE (0) /* No EEPROM */
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# undef LPC43_NLCD /* No LCD controller */
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# define LPC43_ETHERNET (1) /* One Ethernet controller */
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# define LPC43_USB0 (1) /* Have USB0 (Host, Device, OTG) */
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# define LPC43_USB1 (1) /* Have USB1 (Host, Device) */
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# undef LPC43_USB1_ULPI /* No USB1 (Host, Device) with ULPI I/F */
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# define LPC43_MCPWM (1) /* One PWM interface */
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# undef LPC43_QEI /* No Quadrature Encoder capability */
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# define LPC43_NUSARTS (4) /* Three USARTs + 1 UART */
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# define LPC43_NSSP (2) /* Two SSP controllers */
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# define LPC43_NTIMERS (4) /* Four Timers */
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# define LPC43_NI2C (2) /* Two I2C controllers */
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# define LPC43_NI2S (2) /* Two I2S controllers */
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# define LPC43_NCAN (2) /* Two CAN controllers */
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# define LPC43_NDAC (1) /* One 10-bit DAC */
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# define LPC43_NADC10 (2) /* Two 10-bit ADC controllers */
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# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
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# undef LPC43_NADC12 /* No 12-bit ADC controllers */
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#elif defined(CONFIG_ARCH_CHIP_LPC4330FET100)
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# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
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# define LPC43_FLASH_BANKB_SIZE (0)
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# define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 200Kb Local SRAM*/
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# define LPC43_LOCSRAM_BANK1_SIZE (72*1024)
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# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
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# define LPC43_AHBSRAM_BANK1_SIZE (0)
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# define LPC43_AHBSRAM_BANK2_SIZE (16*1024)
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# define LPC43_EEPROM_SIZE (0) /* No EEPROM */
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# undef LPC43_NLCD /* No LCD controller */
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# define LPC43_ETHERNET (1) /* One Ethernet controller */
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# define LPC43_USB0 (1) /* Have USB0 (Host, Device, OTG) */
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# define LPC43_USB1 (1) /* Have USB1 (Host, Device) */
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# undef LPC43_USB1_ULPI /* No USB1 (Host, Device) with ULPI I/F */
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# undef LPC43_MCPWM /* No PWM capability */
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# undef LPC43_QEI /* No Quadrature Encoder capability */
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# define LPC43_NUSARTS (4) /* Three USARTs + 1 UART */
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# define LPC43_NSSP (2) /* Two SSP controllers */
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# define LPC43_NTIMERS (4) /* Four Timers */
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# define LPC43_NI2C (2) /* Two I2C controllers */
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# define LPC43_NI2S (2) /* Two I2S controllers */
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# define LPC43_NCAN (2) /* Two CAN controllers */
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# define LPC43_NDAC (1) /* One 10-bit DAC */
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# define LPC43_NADC10 (2) /* Two 10-bit ADC controllers */
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# define LPC43_NADC10_CHANNELS (4) /* Four ADC channels */
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# undef LPC43_NADC12 /* No 12-bit ADC controllers */
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#elif defined(CONFIG_ARCH_CHIP_LPC4330FET180)
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# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
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# define LPC43_FLASH_BANKB_SIZE (0)
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# define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 200Kb Local SRAM*/
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# define LPC43_LOCSRAM_BANK1_SIZE (72*1024)
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# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
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# define LPC43_AHBSRAM_BANK1_SIZE (0)
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# define LPC43_AHBSRAM_BANK2_SIZE (16*1024)
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# define LPC43_EEPROM_SIZE (0) /* No EEPROM */
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# undef LPC43_NLCD /* No LCD controller */
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# define LPC43_ETHERNET (1) /* One Ethernet controller */
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# define LPC43_USB0 (1) /* Have USB0 (Host, Device, OTG) */
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# define LPC43_USB1 (1) /* Have USB1 (Host, Device) */
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# define LPC43_USB1_ULPI (1) /* Have USB1 (Host, Device) with ULPI I/F */
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# define LPC43_MCPWM (1) /* One PWM interface */
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# define LPC43_QEI (1) /* One Quadrature Encoder interface */
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# define LPC43_NUSARTS (4) /* Three USARTs + 1 UART */
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# define LPC43_NSSP (2) /* Two SSP controllers */
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# define LPC43_NTIMERS (4) /* Four Timers */
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# define LPC43_NI2C (2) /* Two I2C controllers */
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# define LPC43_NI2S (2) /* Two I2S controllers */
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# define LPC43_NCAN (2) /* Two CAN controllers */
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# define LPC43_NDAC (1) /* One 10-bit DAC */
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# define LPC43_NADC10 (2) /* Two 10-bit ADC controllers */
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# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
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# undef LPC43_NADC12 /* No 12-bit ADC controllers */
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#elif defined(CONFIG_ARCH_CHIP_LPC4330FET256)
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# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
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# define LPC43_FLASH_BANKB_SIZE (0)
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# define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 200Kb Local SRAM*/
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# define LPC43_LOCSRAM_BANK1_SIZE (72*1024)
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# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
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# define LPC43_AHBSRAM_BANK1_SIZE (0)
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# define LPC43_AHBSRAM_BANK2_SIZE (16*1024)
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# define LPC43_EEPROM_SIZE (0) /* No EEPROM */
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# undef LPC43_NLCD /* No LCD controller */
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# define LPC43_ETHERNET (1) /* One Ethernet controller */
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# define LPC43_USB0 (1) /* Have USB0 (Host, Device, OTG) */
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# define LPC43_USB1 (1) /* Have USB1 (Host, Device) */
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# define LPC43_USB1_ULPI (1) /* Have USB1 (Host, Device) with ULPI I/F */
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# define LPC43_MCPWM (1) /* One PWM interface */
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# define LPC43_QEI (1) /* One Quadrature Encoder interface */
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# define LPC43_NUSARTS (4) /* Three USARTs + 1 UART */
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# define LPC43_NSSP (2) /* Two SSP controllers */
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# define LPC43_NTIMERS (4) /* Four Timers */
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# define LPC43_NI2C (2) /* Two I2C controllers */
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# define LPC43_NI2S (2) /* Two I2S controllers */
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# define LPC43_NCAN (2) /* Two CAN controllers */
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# define LPC43_NDAC (1) /* One 10-bit DAC */
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# define LPC43_NADC10 (2) /* Two 10-bit ADC controllers */
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# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
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# undef LPC43_NADC12 /* No 12-bit ADC controllers */
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#elif defined(CONFIG_ARCH_CHIP_LPC4337JBD144)
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# define LPC43_FLASH_BANKA_SIZE (512*1025) /* 1024Kb FLASH */
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# define LPC43_FLASH_BANKB_SIZE (512*1025)
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# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM*/
|
|
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
|
|
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
|
|
# define LPC43_AHBSRAM_BANK1_SIZE (0)
|
|
# define LPC43_AHBSRAM_BANK2_SIZE (16*1024)
|
|
# define LPC43_EEPROM_SIZE (16*1024) /* 16Kb EEPROM */
|
|
# define LPC43_NLCD (0) /* Has LCD controller */
|
|
# define LPC43_ETHERNET (1) /* One Ethernet controller */
|
|
# define LPC43_USB0 (1) /* Have USB0 (Host, Device, OTG) */
|
|
# define LPC43_USB1 (1) /* Have USB1 (Host, Device) */
|
|
# define LPC43_USB1_ULPI (0) /* Have USB1 (Host, Device) with ULPI I/F */
|
|
# define LPC43_MCPWM (1) /* One PWM interface */
|
|
# define LPC43_QEI (0) /* One Quadrature Encoder interface */
|
|
# define LPC43_NUSARTS (4) /* Three USARTs + 1 UART */
|
|
# define LPC43_NSSP (2) /* Two SSP controllers */
|
|
# define LPC43_NTIMERS (4) /* Four Timers */
|
|
# define LPC43_NI2C (2) /* Two I2C controllers */
|
|
# define LPC43_NI2S (2) /* Two I2S controllers */
|
|
# define LPC43_NCAN (2) /* Two CAN controllers */
|
|
# define LPC43_NDAC (1) /* One 10-bit DAC */
|
|
# define LPC43_NADC10 (2) /* Two 10-bit ADC controllers */
|
|
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
|
|
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
|
|
#elif defined(CONFIG_ARCH_CHIP_LPC4350FBD208)
|
|
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
|
|
# define LPC43_FLASH_BANKB_SIZE (0)
|
|
# define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 200Kb Local SRAM*/
|
|
# define LPC43_LOCSRAM_BANK1_SIZE (72*1024)
|
|
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
|
|
# define LPC43_AHBSRAM_BANK1_SIZE (0)
|
|
# define LPC43_AHBSRAM_BANK2_SIZE (16*1024)
|
|
# define LPC43_EEPROM_SIZE (0) /* No EEPROM */
|
|
# define LPC43_NLCD (1) /* One LCD controller */
|
|
# define LPC43_ETHERNET (1) /* One Ethernet controller */
|
|
# define LPC43_USB0 (1) /* Have USB0 (Host, Device, OTG) */
|
|
# define LPC43_USB1 (1) /* Have USB1 (Host, Device) */
|
|
# define LPC43_USB1_ULPI (1) /* Have USB1 (Host, Device) with ULPI I/F */
|
|
# define LPC43_MCPWM (1) /* One PWM interface */
|
|
# define LPC43_QEI (1) /* One Quadrature Encoder interface */
|
|
# define LPC43_NUSARTS (4) /* Three USARTs + 1 UART */
|
|
# define LPC43_NSSP (2) /* Two SSP controllers */
|
|
# define LPC43_NTIMERS (4) /* Four Timers */
|
|
# define LPC43_NI2C (2) /* Two I2C controllers */
|
|
# define LPC43_NI2S (2) /* Two I2S controllers */
|
|
# define LPC43_NCAN (2) /* Two CAN controllers */
|
|
# define LPC43_NDAC (1) /* One 10-bit DAC */
|
|
# define LPC43_NADC10 (2) /* Two 10-bit ADC controllers */
|
|
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
|
|
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
|
|
#elif defined(CONFIG_ARCH_CHIP_LPC4350FET180)
|
|
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
|
|
# define LPC43_FLASH_BANKB_SIZE (0)
|
|
# define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 200Kb Local SRAM*/
|
|
# define LPC43_LOCSRAM_BANK1_SIZE (72*1024)
|
|
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
|
|
# define LPC43_AHBSRAM_BANK1_SIZE (0)
|
|
# define LPC43_AHBSRAM_BANK2_SIZE (16*1024)
|
|
# define LPC43_EEPROM_SIZE (0) /* No EEPROM */
|
|
# define LPC43_NLCD (1) /* One LCD controller */
|
|
# define LPC43_ETHERNET (1) /* One Ethernet controller */
|
|
# define LPC43_USB0 (1) /* Have USB0 (Host, Device, OTG) */
|
|
# define LPC43_USB1 (1) /* Have USB1 (Host, Device) */
|
|
# define LPC43_USB1_ULPI (1) /* Have USB1 (Host, Device) with ULPI I/F */
|
|
# define LPC43_MCPWM (1) /* One PWM interface */
|
|
# define LPC43_QEI (1) /* One Quadrature Encoder interface */
|
|
# define LPC43_NUSARTS (4) /* Three USARTs + 1 UART */
|
|
# define LPC43_NSSP (2) /* Two SSP controllers */
|
|
# define LPC43_NTIMERS (4) /* Four Timers */
|
|
# define LPC43_NI2C (2) /* Two I2C controllers */
|
|
# define LPC43_NI2S (2) /* Two I2S controllers */
|
|
# define LPC43_NCAN (2) /* Two CAN controllers */
|
|
# define LPC43_NDAC (1) /* One 10-bit DAC */
|
|
# define LPC43_NADC10 (2) /* Two 10-bit ADC controllers */
|
|
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
|
|
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
|
|
#elif defined(CONFIG_ARCH_CHIP_LPC4350FET256)
|
|
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
|
|
# define LPC43_FLASH_BANKB_SIZE (0)
|
|
# define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 200Kb Local SRAM*/
|
|
# define LPC43_LOCSRAM_BANK1_SIZE (72*1024)
|
|
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
|
|
# define LPC43_AHBSRAM_BANK1_SIZE (0)
|
|
# define LPC43_AHBSRAM_BANK2_SIZE (16*1024)
|
|
# define LPC43_EEPROM_SIZE (0) /* No EEPROM */
|
|
# define LPC43_NLCD (1) /* One LCD controller */
|
|
# define LPC43_ETHERNET (1) /* One Ethernet controller */
|
|
# define LPC43_USB0 (1) /* Have USB0 (Host, Device, OTG) */
|
|
# define LPC43_USB1 (1) /* Have USB1 (Host, Device) */
|
|
# define LPC43_USB1_ULPI (1) /* Have USB1 (Host, Device) with ULPI I/F */
|
|
# define LPC43_MCPWM (1) /* One PWM interface */
|
|
# define LPC43_QEI (1) /* One Quadrature Encoder interface */
|
|
# define LPC43_NUSARTS (4) /* Three USARTs + 1 UART */
|
|
# define LPC43_NSSP (2) /* Two SSP controllers */
|
|
# define LPC43_NTIMERS (4) /* Four Timers */
|
|
# define LPC43_NI2C (2) /* Two I2C controllers */
|
|
# define LPC43_NI2S (2) /* Two I2S controllers */
|
|
# define LPC43_NCAN (2) /* Two CAN controllers */
|
|
# define LPC43_NDAC (1) /* One 10-bit DAC */
|
|
# define LPC43_NADC10 (2) /* Two 10-bit ADC controllers */
|
|
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
|
|
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
|
|
#elif defined(CONFIG_ARCH_CHIP_LPC4353FBD208)
|
|
# define LPC43_FLASH_BANKA_SIZE (256*1025) /* 512Kb FLASH */
|
|
# define LPC43_FLASH_BANKB_SIZE (256*1025)
|
|
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM*/
|
|
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
|
|
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
|
|
# define LPC43_AHBSRAM_BANK1_SIZE (0)
|
|
# define LPC43_AHBSRAM_BANK2_SIZE (16*1024)
|
|
# define LPC43_EEPROM_SIZE (16*1024) /* 16Kb EEPROM */
|
|
# define LPC43_NLCD (1) /* Has LCD controller */
|
|
# define LPC43_ETHERNET (1) /* One Ethernet controller */
|
|
# define LPC43_USB0 (1) /* Have USB0 (Host, Device, OTG) */
|
|
# define LPC43_USB1 (1) /* Have USB1 (Host, Device) */
|
|
# define LPC43_USB1_ULPI (1) /* Have USB1 (Host, Device) with ULPI I/F */
|
|
# define LPC43_MCPWM (1) /* One PWM interface */
|
|
# define LPC43_QEI (1) /* One Quadrature Encoder interface */
|
|
# define LPC43_NUSARTS (4) /* Three USARTs + 1 UART */
|
|
# define LPC43_NSSP (2) /* Two SSP controllers */
|
|
# define LPC43_NTIMERS (4) /* Four Timers */
|
|
# define LPC43_NI2C (2) /* Two I2C controllers */
|
|
# define LPC43_NI2S (2) /* Two I2S controllers */
|
|
# define LPC43_NCAN (2) /* Two CAN controllers */
|
|
# define LPC43_NDAC (1) /* One 10-bit DAC */
|
|
# define LPC43_NADC10 (2) /* Two 10-bit ADC controllers */
|
|
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
|
|
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
|
|
#elif defined(CONFIG_ARCH_CHIP_LPC4353FET180)
|
|
# define LPC43_FLASH_BANKA_SIZE (256*1025) /* 512Kb FLASH */
|
|
# define LPC43_FLASH_BANKB_SIZE (256*1025)
|
|
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM*/
|
|
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
|
|
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
|
|
# define LPC43_AHBSRAM_BANK1_SIZE (0)
|
|
# define LPC43_AHBSRAM_BANK2_SIZE (16*1024)
|
|
# define LPC43_EEPROM_SIZE (16*1024) /* 16Kb EEPROM */
|
|
# define LPC43_NLCD (1) /* Has LCD controller */
|
|
# define LPC43_ETHERNET (1) /* One Ethernet controller */
|
|
# define LPC43_USB0 (1) /* Have USB0 (Host, Device, OTG) */
|
|
# define LPC43_USB1 (1) /* Have USB1 (Host, Device) */
|
|
# define LPC43_USB1_ULPI (1) /* Have USB1 (Host, Device) with ULPI I/F */
|
|
# define LPC43_MCPWM (1) /* One PWM interface */
|
|
# define LPC43_QEI (1) /* One Quadrature Encoder interface */
|
|
# define LPC43_NUSARTS (4) /* Three USARTs + 1 UART */
|
|
# define LPC43_NSSP (2) /* Two SSP controllers */
|
|
# define LPC43_NTIMERS (4) /* Four Timers */
|
|
# define LPC43_NI2C (2) /* Two I2C controllers */
|
|
# define LPC43_NI2S (2) /* Two I2S controllers */
|
|
# define LPC43_NCAN (2) /* Two CAN controllers */
|
|
# define LPC43_NDAC (1) /* One 10-bit DAC */
|
|
# define LPC43_NADC10 (2) /* Two 10-bit ADC controllers */
|
|
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
|
|
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
|
|
#elif defined(CONFIG_ARCH_CHIP_LPC4353FET256)
|
|
# define LPC43_FLASH_BANKA_SIZE (256*1025) /* 512Kb FLASH */
|
|
# define LPC43_FLASH_BANKB_SIZE (256*1025)
|
|
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM*/
|
|
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
|
|
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
|
|
# define LPC43_AHBSRAM_BANK1_SIZE (0)
|
|
# define LPC43_AHBSRAM_BANK2_SIZE (16*1024)
|
|
# define LPC43_EEPROM_SIZE (16*1024) /* 16Kb EEPROM */
|
|
# define LPC43_NLCD (1) /* Has LCD controller */
|
|
# define LPC43_ETHERNET (1) /* One Ethernet controller */
|
|
# define LPC43_USB0 (1) /* Have USB0 (Host, Device, OTG) */
|
|
# define LPC43_USB1 (1) /* Have USB1 (Host, Device) */
|
|
# define LPC43_USB1_ULPI (1) /* Have USB1 (Host, Device) with ULPI I/F */
|
|
# define LPC43_MCPWM (1) /* One PWM interface */
|
|
# define LPC43_QEI (1) /* One Quadrature Encoder interface */
|
|
# define LPC43_NUSARTS (4) /* Three USARTs + 1 UART */
|
|
# define LPC43_NSSP (2) /* Two SSP controllers */
|
|
# define LPC43_NTIMERS (4) /* Four Timers */
|
|
# define LPC43_NI2C (2) /* Two I2C controllers */
|
|
# define LPC43_NI2S (2) /* Two I2S controllers */
|
|
# define LPC43_NCAN (2) /* Two CAN controllers */
|
|
# define LPC43_NDAC (1) /* One 10-bit DAC */
|
|
# define LPC43_NADC10 (2) /* Two 10-bit ADC controllers */
|
|
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
|
|
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
|
|
#elif defined(CONFIG_ARCH_CHIP_LPC4357FET180)
|
|
# define LPC43_FLASH_BANKA_SIZE (512*1025) /* 1024Kb FLASH */
|
|
# define LPC43_FLASH_BANKB_SIZE (512*1025)
|
|
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM*/
|
|
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
|
|
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
|
|
# define LPC43_AHBSRAM_BANK1_SIZE (0)
|
|
# define LPC43_AHBSRAM_BANK2_SIZE (16*1024)
|
|
# define LPC43_EEPROM_SIZE (16*1024) /* 16Kb EEPROM */
|
|
# define LPC43_NLCD (1) /* Has LCD controller */
|
|
# define LPC43_ETHERNET (1) /* One Ethernet controller */
|
|
# define LPC43_USB0 (1) /* Have USB0 (Host, Device, OTG) */
|
|
# define LPC43_USB1 (1) /* Have USB1 (Host, Device) */
|
|
# define LPC43_USB1_ULPI (1) /* Have USB1 (Host, Device) with ULPI I/F */
|
|
# define LPC43_MCPWM (1) /* One PWM interface */
|
|
# define LPC43_QEI (1) /* One Quadrature Encoder interface */
|
|
# define LPC43_NUSARTS (4) /* Three USARTs + 1 UART */
|
|
# define LPC43_NSSP (2) /* Two SSP controllers */
|
|
# define LPC43_NTIMERS (4) /* Four Timers */
|
|
# define LPC43_NI2C (2) /* Two I2C controllers */
|
|
# define LPC43_NI2S (2) /* Two I2S controllers */
|
|
# define LPC43_NCAN (2) /* Two CAN controllers */
|
|
# define LPC43_NDAC (1) /* One 10-bit DAC */
|
|
# define LPC43_NADC10 (2) /* Two 10-bit ADC controllers */
|
|
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
|
|
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
|
|
#elif defined(CONFIG_ARCH_CHIP_LPC4357FBD208)
|
|
# define LPC43_FLASH_BANKA_SIZE (512*1025) /* 1024Kb FLASH */
|
|
# define LPC43_FLASH_BANKB_SIZE (512*1025)
|
|
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM*/
|
|
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
|
|
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
|
|
# define LPC43_AHBSRAM_BANK1_SIZE (0)
|
|
# define LPC43_AHBSRAM_BANK2_SIZE (16*1024)
|
|
# define LPC43_EEPROM_SIZE (16*1024) /* 16Kb EEPROM */
|
|
# define LPC43_NLCD (1) /* Has LCD controller */
|
|
# define LPC43_ETHERNET (1) /* One Ethernet controller */
|
|
# define LPC43_USB0 (1) /* Have USB0 (Host, Device, OTG) */
|
|
# define LPC43_USB1 (1) /* Have USB1 (Host, Device) */
|
|
# define LPC43_USB1_ULPI (1) /* Have USB1 (Host, Device) with ULPI I/F */
|
|
# define LPC43_MCPWM (1) /* One PWM interface */
|
|
# define LPC43_QEI (1) /* One Quadrature Encoder interface */
|
|
# define LPC43_NUSARTS (4) /* Three USARTs + 1 UART */
|
|
# define LPC43_NSSP (2) /* Two SSP controllers */
|
|
# define LPC43_NTIMERS (4) /* Four Timers */
|
|
# define LPC43_NI2C (2) /* Two I2C controllers */
|
|
# define LPC43_NI2S (2) /* Two I2S controllers */
|
|
# define LPC43_NCAN (2) /* Two CAN controllers */
|
|
# define LPC43_NDAC (1) /* One 10-bit DAC */
|
|
# define LPC43_NADC10 (2) /* Two 10-bit ADC controllers */
|
|
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
|
|
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
|
|
#elif defined(CONFIG_ARCH_CHIP_LPC4357FET256)
|
|
# define LPC43_FLASH_BANKA_SIZE (512*1025) /* 1024Kb FLASH */
|
|
# define LPC43_FLASH_BANKB_SIZE (512*1025)
|
|
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM*/
|
|
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
|
|
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
|
|
# define LPC43_AHBSRAM_BANK1_SIZE (0)
|
|
# define LPC43_AHBSRAM_BANK2_SIZE (16*1024)
|
|
# define LPC43_EEPROM_SIZE (16*1024) /* 16Kb EEPROM */
|
|
# define LPC43_NLCD (1) /* Has LCD controller */
|
|
# define LPC43_ETHERNET (1) /* One Ethernet controller */
|
|
# define LPC43_USB0 (1) /* Have USB0 (Host, Device, OTG) */
|
|
# define LPC43_USB1 (1) /* Have USB1 (Host, Device) */
|
|
# define LPC43_USB1_ULPI (1) /* Have USB1 (Host, Device) with ULPI I/F */
|
|
# define LPC43_MCPWM (1) /* One PWM interface */
|
|
# define LPC43_QEI (1) /* One Quadrature Encoder interface */
|
|
# define LPC43_NUSARTS (4) /* Three USARTs + 1 UART */
|
|
# define LPC43_NSSP (2) /* Two SSP controllers */
|
|
# define LPC43_NTIMERS (4) /* Four Timers */
|
|
# define LPC43_NI2C (2) /* Two I2C controllers */
|
|
# define LPC43_NI2S (2) /* Two I2S controllers */
|
|
# define LPC43_NCAN (2) /* Two CAN controllers */
|
|
# define LPC43_NDAC (1) /* One 10-bit DAC */
|
|
# define LPC43_NADC10 (2) /* Two 10-bit ADC controllers */
|
|
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
|
|
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
|
|
#elif defined(CONFIG_ARCH_CHIP_LPC4370FET100)
|
|
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
|
|
# define LPC43_FLASH_BANKB_SIZE (0)
|
|
# define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 200Kb Local SRAM (plus 18Kb for Cortex-M0)*/
|
|
# define LPC43_LOCSRAM_BANK1_SIZE (72*1024)
|
|
# define LPC43_AHBSRAM_BANK0_SIZE (32*1024) /* 64Kb AHB SRAM */
|
|
# define LPC43_AHBSRAM_BANK1_SIZE (16*1024)
|
|
# define LPC43_AHBSRAM_BANK2_SIZE (16*1024)
|
|
# define LPC43_EEPROM_SIZE (0) /* No EEPROM */
|
|
# undef LPC43_NLCD /* No LCD controller */
|
|
# define LPC43_ETHERNET (1) /* One Ethernet controller */
|
|
# define LPC43_USB0 (1) /* Have USB0 (Host, Device, OTG) */
|
|
# define LPC43_USB1 (1) /* Have USB1 (Host, Device) */
|
|
# undef LPC43_USB1_ULPI /* No USB1 (Host, Device) with ULPI I/F */
|
|
# undef LPC43_MCPWM /* No PWM capability */
|
|
# undef LPC43_QEI /* No Quadrature Encoder capability */
|
|
# define LPC43_NUSARTS (4) /* Three USARTs + 1 UART */
|
|
# define LPC43_NSSP (2) /* Two SSP controllers */
|
|
# define LPC43_NTIMERS (4) /* Four Timers */
|
|
# define LPC43_NI2C (2) /* Two I2C controllers */
|
|
# define LPC43_NI2S (2) /* Two I2S controllers */
|
|
# define LPC43_NCAN (2) /* Two C-CAN controllers */
|
|
# define LPC43_NDAC (1) /* One 10-bit DAC */
|
|
# define LPC43_NADC10 (2) /* Two 10-bit ADC controllers */
|
|
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels (per ADC)*/
|
|
# define LPC43_NADC12 (1) /* ONne 12-bit ADC controllers (ADCHS)*/
|
|
#elif defined(CONFIG_ARCH_CHIP_LPC4370FET256)
|
|
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
|
|
# define LPC43_FLASH_BANKB_SIZE (0)
|
|
# define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 200Kb Local SRAM (plus 18Kb for Cortex-M0)*/
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# define LPC43_LOCSRAM_BANK1_SIZE (72*1024)
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# define LPC43_AHBSRAM_BANK0_SIZE (32*1024) /* 64Kb AHB SRAM */
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# define LPC43_AHBSRAM_BANK1_SIZE (16*1024)
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# define LPC43_AHBSRAM_BANK2_SIZE (16*1024)
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# define LPC43_EEPROM_SIZE (0) /* No EEPROM */
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# define LPC43_NLCD (1) /* One LCD controller */
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# define LPC43_ETHERNET (1) /* One Ethernet controller */
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# define LPC43_USB0 (1) /* Have USB0 (Host, Device, OTG) */
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# define LPC43_USB1 (1) /* Have USB1 (Host, Device) */
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# define LPC43_USB1_ULPI (1) /* Have USB1 (Host, Device) with ULPI I/F */
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# define LPC43_MCPWM (1) /* One PWM interface */
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# define LPC43_QEI (1) /* One Quadrature Encoder interface */
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# define LPC43_NUSARTS (4) /* Three USARTs + 1 UART */
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# define LPC43_NSSP (2) /* Two SSP controllers */
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# define LPC43_NTIMERS (4) /* Four Timers */
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# define LPC43_NI2C (2) /* Two I2C controllers */
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# define LPC43_NI2S (2) /* Two I2S controllers */
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# define LPC43_NCAN (2) /* Two C-CAN controllers */
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# define LPC43_NDAC (1) /* One 10-bit DAC */
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# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels (per ADC)*/
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# define LPC43_NADC12 (1) /* ONne 12-bit ADC controllers (ADCHS)*/
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#else
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# error "Unsupported LPC43xx chip"
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#endif
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/* NVIC priority levels *************************************************************/
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/* Each priority field holds a priority value, 0-31. The lower the value, the greater
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* the priority of the corresponding interrupt.
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*
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* The Cortex-M4 core supports up to 53 interrupts an 8 prgrammable interrupt
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* priority levels; The Cortex-M0 core supports up to 32 interrupts with 4
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* programmable interrupt priorities.
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*/
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#define LPC43M4_SYSH_PRIORITY_MIN 0xe0 /* All bits[7:5] set is minimum priority */
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#define LPC43M4_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
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#define LPC43M4_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
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#define LPC43M4_SYSH_PRIORITY_STEP 0x20 /* Steps between priorities */
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#define LPC43M0_SYSH_PRIORITY_MIN 0xc0 /* All bits[7:6] set is minimum priority */
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#define LPC43M0_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
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#define LPC43M0_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
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#define LPC43M0_SYSH_PRIORITY_STEP 0x40 /* Steps between priorities */
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/* Only the Cortex-M4 is supported by Nuttx */
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#define NVIC_SYSH_PRIORITY_MIN LPC43M4_SYSH_PRIORITY_MIN
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#define NVIC_SYSH_PRIORITY_DEFAULT LPC43M4_SYSH_PRIORITY_DEFAULT
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#define NVIC_SYSH_PRIORITY_MAX LPC43M4_SYSH_PRIORITY_MAX
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#define NVIC_SYSH_PRIORITY_STEP LPC43M4_SYSH_PRIORITY_STEP
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|
|
|
/* If CONFIG_ARMV7M_USEBASEPRI is selected, then interrupts will be disabled
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|
* by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so that most
|
|
* interrupts will not have execution priority. SVCall must have execution
|
|
* priority in all cases.
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|
*
|
|
* In the normal cases, interrupts are not nest-able and all interrupts run
|
|
* at an execution priority between NVIC_SYSH_PRIORITY_MIN and
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* NVIC_SYSH_PRIORITY_MAX (with NVIC_SYSH_PRIORITY_MAX reserved for SVCall).
|
|
*
|
|
* If, in addition, CONFIG_ARCH_HIPRI_INTERRUPT is defined, then special
|
|
* high priority interrupts are supported. These are not "nested" in the
|
|
* normal sense of the word. These high priority interrupts can interrupt
|
|
* normal processing but execute outside of OS (although they can "get back
|
|
* into the game" via a PendSV interrupt).
|
|
*
|
|
* In the normal course of things, interrupts must occasionally be disabled
|
|
* using the up_irq_save() inline function to prevent contention in use of
|
|
* resources that may be shared between interrupt level and non-interrupt
|
|
* level logic. Now the question arises, if CONFIG_ARCH_HIPRI_INTERRUPT,
|
|
* do we disable all interrupts (except SVCall), or do we only disable the
|
|
* "normal" interrupts. Since the high priority interrupts cannot interact
|
|
* with the OS, you may want to permit the high priority interrupts even if
|
|
* interrupts are disabled. The setting CONFIG_ARCH_INT_DISABLEALL can be
|
|
* used to select either behavior:
|
|
*
|
|
* ----------------------------+--------------+----------------------------
|
|
* CONFIG_ARCH_HIPRI_INTERRUPT | NO | YES
|
|
* ----------------------------+--------------+--------------+-------------
|
|
* CONFIG_ARCH_INT_DISABLEALL | N/A | YES | NO
|
|
* ----------------------------+--------------+--------------+-------------
|
|
* | | | SVCall
|
|
* | SVCall | SVCall | HIGH
|
|
* Disable here and below --------> MAXNORMAL ---> HIGH --------> MAXNORMAL
|
|
* | | MAXNORMAL |
|
|
* ----------------------------+--------------+--------------+-------------
|
|
*/
|
|
|
|
#if defined(CONFIG_ARCH_HIPRI_INTERRUPT) && defined(CONFIG_ARCH_INT_DISABLEALL)
|
|
# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + 2*NVIC_SYSH_PRIORITY_STEP)
|
|
# define NVIC_SYSH_HIGH_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP)
|
|
# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_HIGH_PRIORITY
|
|
# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX
|
|
#else
|
|
# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP)
|
|
# define NVIC_SYSH_HIGH_PRIORITY NVIC_SYSH_PRIORITY_MAX
|
|
# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_MAXNORMAL_PRIORITY
|
|
# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX
|
|
#endif
|
|
|
|
/************************************************************************************
|
|
* Public Types
|
|
************************************************************************************/
|
|
|
|
/************************************************************************************
|
|
* Public Data
|
|
************************************************************************************/
|
|
|
|
/************************************************************************************
|
|
* Public Functions
|
|
************************************************************************************/
|
|
|
|
#endif /* __ARCH_ARM_INCLUDE_LPC43XX_CHIP_H */
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