487 lines
17 KiB
C
487 lines
17 KiB
C
/****************************************************************************
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* boards/arm/lpc17xx_40xx/lx_cpu/include/board.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __BOARDS_ARM_LPC17XX_40XX_LX_CPU_INCLUDE_BOARD_H
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#define __BOARDS_ARM_LPC17XX_40XX_LX_CPU_INCLUDE_BOARD_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdbool.h>
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#if defined(CONFIG_ARCH_IRQBUTTONS) && defined(CONFIG_LPC17_40_GPIOIRQ)
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# include <nuttx/irq.h>
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Clocking *****************************************************************/
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/* NOTE:
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* The following definitions require lpc17_40_syscon.h.
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* It is not included here because the including C file may not have that
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* file in its include path.
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*/
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#define BOARD_XTAL_FREQUENCY (12000000) /* XTAL oscillator frequency */
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#define BOARD_OSCCLK_FREQUENCY BOARD_XTAL_FREQUENCY /* Main oscillator frequency */
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#define BOARD_RTCCLK_FREQUENCY (32768) /* RTC oscillator frequency */
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#define BOARD_INTRCOSC_FREQUENCY (4000000) /* Internal RC oscillator frequency */
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#define BOARD_WDTOSC_FREQUENCY (500000) /* WDT oscillator frequency */
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/* This is the clock setup we configure for:
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*
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* SYSCLK = BOARD_OSCCLK_FREQUENCY = 12MHz -> Select Main oscillator for
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* source
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* PLL0CLK = (12 * SYSCLK) / 1 = 144MHz -> PLL0 multipler=12, pre-divider=1
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* CCLCK = 72MHz -> CCLK divider = 2
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*/
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#define LPC17_40_CCLK 72000000 /* 72Mhz */
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#define BOARD_PCLKDIV 2 /* Peripheral clock = LPC17_40_CCLK/2 */
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#define BOARD_PCLK_FREQUENCY (LPC17_40_CCLK * BOARD_CCLKSEL_DIVIDER / BOARD_PCLKDIV)
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/* Select the main oscillator as the frequency source.
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* SYSCLK is then the frequency of the main oscillator.
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*
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* If BOARD_XTAL_FREQUENCY > 15000000, then the SCS OSCRS bit (bit 4) should
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* also be set in the BOARD_SCS_VALUE.
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*/
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#undef CONFIG_LPC17_40_MAINOSC
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#define CONFIG_LPC17_40_MAINOSC 1
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#define BOARD_SCS_VALUE SYSCON_SCS_OSCEN
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/* Select the main oscillator and CCLK divider.
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* The output of the divider is CCLK.
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* The input to the divider (PLLCLK) will be determined by the PLL output.
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*/
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#define BOARD_CCLKSEL_DIVIDER 2
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#define BOARD_CCLKSEL_VALUE (BOARD_CCLKSEL_DIVIDER | SYSCON_CCLKSEL_CCLKSEL)
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/* PLL0. PLL0 is used to generate the CPU clock (PLLCLK).
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*
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* Source clock: Main oscillator
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* PLL0 Multiplier value (M): 12
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* PLL0 Pre-divider value (P): 1
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*
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* PLL0CLK = (M * SYSCLK) = 144MHz
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*/
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#undef CONFIG_LPC17_40_PLL0
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#define CONFIG_LPC17_40_PLL0 1
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#define BOARD_CLKSRCSEL_VALUE SYSCON_CLKSRCSEL_MAIN
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#define BOARD_PLL0CFG_MSEL 12
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#define BOARD_PLL0CFG_PSEL 1
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#define BOARD_PLL0CFG_VALUE \
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(((BOARD_PLL0CFG_MSEL-1) << SYSCON_PLLCFG_MSEL_SHIFT) | \
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((BOARD_PLL0CFG_PSEL-1) << SYSCON_PLLCFG_PSEL_SHIFT))
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/* PLL1 : PLL1 is used to generate clock for the USB */
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#undef CONFIG_LPC17_40_PLL1
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#define BOARD_PLL1CFG_MSEL 4
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#define BOARD_PLL1CFG_PSEL 2
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#define BOARD_PLL1CFG_VALUE \
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(((BOARD_PLL1CFG_MSEL-1) << SYSCON_PLLCFG_MSEL_SHIFT) | \
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((BOARD_PLL1CFG_PSEL-1) << SYSCON_PLLCFG_PSEL_SHIFT))
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#ifdef CONFIG_LPC17_40_EMC
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/* EMC clock selection.
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*
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* The EMC clock should not be driven above 80MHz. As a result the EMC
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* uses the CPU clock divided by two.
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*/
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# define BOARD_EMCCLKSEL_DIVIDER 1
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# define BOARD_EMCCLKSEL_VALUE SYSCON_EMCCLKSEL_CCLK_DIV1
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# define LPC17_40_EMCCLK (LPC17_40_CCLK / BOARD_EMCCLKSEL_DIVIDER)
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# define BOARD_EMC_FPGA_SETUP
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# define BOARD_XC_PROGRAM_PIN (GPIO_PORT0 | GPIO_PIN8 | GPIO_OUTPUT | GPIO_VALUE_ONE)
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# define BOARD_XC_DONE_PIN (GPIO_PORT0 | GPIO_PIN9 | GPIO_INPUT | GPIO_PULLUP)
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# define BOARD_XC_INIT_PIN (GPIO_PORT0 | GPIO_PIN18 | GPIO_OUTPUT | GPIO_PULLUP | GPIO_OPEN_DRAIN)
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# define BOARD_XC_SUSPEND_PIN (GPIO_PORT0 | GPIO_PIN20 | GPIO_OUTPUT | GPIO_VALUE_ONE)
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# define BOARD_XC_RDWR_PIN (GPIO_PORT4 | GPIO_PIN16 | GPIO_OUTPUT | GPIO_VALUE_ZERO)
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#endif
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#if defined(CONFIG_LPC17_40_USBHOST) || (CONFIG_LPC17_40_USBDEV)
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/* USB divider. The output of the PLL is used as the USB clock
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*
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* USBCLK = PLL1CLK = (SYSCLK * 4) = 48MHz
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*/
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# define BOARD_USBCLKSEL_DIVIDER 1
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# define BOARD_USBCLKSEL_VALUE (SYSCON_USBCLKSEL_USBDIV_DIV1 | \
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SYSCON_USBCLKSEL_USBSEL_PLL0)
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#endif
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#define GPIO_USB_DP GPIO_USB1DP
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#define GPIO_USB_DM GPIO_USB1DM
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#define GPIO_USB_CONNECT GPIO_USB1_CONNECT
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#define GPIO_USB_OVRCR GPIO_USB2_OVRCR
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#define GPIO_USB_PPWR GPIO_USB_PPWR2
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#define GPIO_USB_PWRD (GPIO_FLOAT | GPIO_PORT2 | GPIO_PIN10)
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#if 0
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# define GPIO_USB_PPWR
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# define GPIO_USB_PWRD
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# define GPIO_USB_OVRCR
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#endif
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/* FLASH Configuration */
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#undef CONFIG_LPC17_40_FLASH
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#define CONFIG_LPC17_40_FLASH 1
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/* Flash access use 4 CPU clocks - Safe for 72 MHz */
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#define BOARD_FLASHCFG_VALUE SYSCON_FLASHCFG_TIM_3
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/* Ethernet configuration */
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#define ETH_MCFG_CLKSEL_DIV ETH_MCFG_CLKSEL_DIV20
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#define GPIO_ENET_CRS (GPIO_ENET_CRSDV)
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#define GPIO_ENET_MDC GPIO_ENET_MDC_1
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#define GPIO_ENET_MDIO GPIO_ENET_MDIO_1
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/* CAN bus configuration */
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#define GPIO_CAN2_RD GPIO_CAN2_RD_1
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#define GPIO_CAN2_TD GPIO_CAN2_TD_1
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#ifdef CONFIG_LPC17_40_SDCARD
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/* SDIO dividers. Note that slower clocking is required when DMA is disabled
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* in order to avoid RX overrun/TX underrun errors due to delayed responses
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* to service FIFOs in interrupt driven mode.
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* SDCARD_CLOCK=PCLK/(2*(SDCARD_CLKDIV+1))
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*/
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# define SDCARD_CLKDIV_INIT 74 /* 400Khz */
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# define SDCARD_INIT_CLKDIV (SDCARD_CLKDIV_INIT)
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# define SDCARD_NORMAL_CLKDIV 1 /* DMA ON: SDCARD_CLOCK=15MHz */
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#define SDCARD_SLOW_CLKDIV 14 /* DMA OFF: SDCARD_CLOCK=2MHz */
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# ifdef CONFIG_SDIO_DMA
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# define SDCARD_MMCXFR_CLKDIV (SDCARD_NORMAL_CLKDIV)
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# else
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# define SDCARD_MMCXFR_CLKDIV (SDCARD_SLOW_CLKDIV)
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# endif
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# ifdef CONFIG_SDIO_DMA
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# define SDCARD_SDXFR_CLKDIV (SDCARD_NORMAL_CLKDIV)
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# else
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# define SDCARD_SDXFR_CLKDIV (SDCARD_SLOW_CLKDIV)
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# endif
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#endif
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/* Set EMC delay values:
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*
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* CMDDLY: Programmable delay value for EMC outputs in command delayed
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* mode. The delay amount is roughly CMDDLY * 250 picoseconds.
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* FBCLKDLY: Programmable delay value for the feedback clock that controls
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* input data sampling. The delay amount is roughly (FBCLKDLY+1) * 250
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* picoseconds.
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* CLKOUT0DLY: Programmable delay value for the CLKOUT0 output. This would
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* typically be used in clock delayed mode. The delay amount is roughly
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* (CLKOUT0DLY+1) * 250 picoseconds.
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* CLKOUT1DLY: Programmable delay value for the CLKOUT1 output. This would
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* typically be used in clock delayed mode. The delay amount is roughly
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* (CLKOUT1DLY+1) * 250 picoseconds.
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*
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* Optimal for NOR: {1,1,1,1}
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* Needed for NAND and SDRAM: {17,1,2,1}
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*/
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#ifdef CONFIG_LPC17_40_EMC
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#if defined(CONFIG_LPC17_40_EXTNAND) || defined(CONFIG_LPC17_40_EXTDRAM)
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# define BOARD_CMDDLY 16
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# define BOARD_FBCLKDLY 16
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# define BOARD_CLKOUT0DLY 1
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# define BOARD_CLKOUT1DLY 1
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#else
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# define BOARD_CMDDLY 1
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# define BOARD_FBCLKDLY 1
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# define BOARD_CLKOUT0DLY 1
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# define BOARD_CLKOUT1DLY 1
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#endif
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#endif
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#define BOARD_NADDR 16
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#define BOARD_NDATA 32
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/* #define BOARD_EMC_CONFIG_BY_LOADER 1 */
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/* LED definitions **********************************************************/
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/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in
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* any way. The following definitions are used to access individual LEDs.
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*
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* LED1 -- Connected to P1[29] RED
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* LED2 -- Connected to P0[16] GREEN
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*
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* These LEDs are connected to ground so a high output value will illuminate
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* them.
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*/
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/* LED index values for use with board_userled() */
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#define BOARD_LED1 0
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#define BOARD_LED2 1
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#define BOARD_NLEDS 2
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/* LED bits for use with board_userled_all() */
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#define BOARD_LED1_BIT (1 << BOARD_LED1)
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#define BOARD_LED2_BIT (1 << BOARD_LED2)
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/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the four LEDs
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* on the WaveShare Open1788K. The following definitions describe how NuttX
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* controls the LEDs:
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*/
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/* LED1 LED2 LED3 LED4 */
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#define LED_STARTED 0 /* OFF OFF OFF OFF */
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#define LED_HEAPALLOCATE 1 /* ON OFF OFF OFF */
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#define LED_IRQSENABLED 2 /* OFF ON OFF OFF */
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#define LED_STACKCREATED 3 /* ON ON OFF OFF */
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#define LED_INIRQ 4 /* LED3 glows, on while in interrupt */
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#define LED_SIGNAL 4 /* LED3 glows, on while in signal handler */
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#define LED_ASSERTION 4 /* LED3 glows, on while in assertion */
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#define LED_PANIC 4 /* LED3 Flashes at 2Hz */
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#define LED_IDLE 5 /* LED4 glows: ON while active *
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* OFF while sleeping */
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/* Button definitions *******************************************************/
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/* The LX_CPU supports several buttons. All must be pulled up by the LX_CPU.
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* When closed, the pins will be pulled to ground.
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* So the buttons will read "1" when open and "0" when closed.
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* All except USER1 are capable of generating interrupts.
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*
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* USER1 -- Connected to P4[26]
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* USER2 -- Connected to P2[22]
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* USER3 -- Connected to P0[10]
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*
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* And a Joystick
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*
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* JOY_A -- Connected to P2[25]
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* JOY_B -- Connected to P2[26]
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* JOY_C -- Connected to P2[23]
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* JOY_D -- Connected to P2[19]
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* JOY_CTR -- Connected to P0[14] (shared with SSP1 SSEL)
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*
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* For the interrupting buttons, interrupts are generated on both edges
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* (press and release).
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*/
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#define BOARD_BUTTON_USER1 0
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#define BOARD_BUTTON_USER2 1
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#define BOARD_BUTTON_USER3 2
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#define BOARD_JOYSTICK_A 3
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#define BOARD_JOYSTICK_B 4
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#define BOARD_JOYSTICK_C 5
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#define BOARD_JOYSTICK_D 6
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#define BOARD_JOYSTICK_CTR 7
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#define NUM_BUTTONS 8
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#define BOARD_BUTTON_USER1_BIT (1 << BOARD_BUTTON_USER1)
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#define BOARD_BUTTON_USER2_BIT (1 << BOARD_BUTTON_USER2)
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#define BOARD_BUTTON_USER3_BIT (1 << BOARD_BUTTON_USER3)
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#define BOARD_JOYSTICK_A_BIT (1 << BOARD_JOYSTICK_A)
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#define BOARD_JOYSTICK_B_BIT (1 << BOARD_JOYSTICK_B)
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#define BOARD_JOYSTICK_C_BIT (1 << BOARD_JOYSTICK_C)
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#define BOARD_JOYSTICK_D_BIT (1 << BOARD_JOYSTICK_D)
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#define BOARD_JOYSTICK_CTR_BIT (1 << BOARD_JOYSTICK_CTR)
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/* Alternate pin selections *************************************************/
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/* UART0:
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*
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* TX --- Connected to P0[2]
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* RX --- Connected to P0[3]
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*/
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#define GPIO_UART0_TXD GPIO_UART0_TXD_2
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#define GPIO_UART0_RXD GPIO_UART0_RXD_2
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/* UART1:
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*
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* All pin options are controlled by older bridges on the bottom of the
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* board.
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* There are the default settings on my board as it came out of the box:
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*
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* RTS --- Connected to P0[22]
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* DSR --- Connected to P0[19]
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* CTS --- Connected to P0[17]
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* TXD --- Connected to P0[15]
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* RXD --- Connected to P0[16] (Shared with LED2)
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*/
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#define GPIO_UART1_RTS GPIO_UART1_RTS_2
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#define GPIO_UART1_DSR GPIO_UART1_DSR_1
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#define GPIO_UART1_CTS GPIO_UART1_CTS_1
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#define GPIO_UART1_TXD GPIO_UART1_TXD_1
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#define GPIO_UART1_RXD GPIO_UART1_RXD_1
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/* MCI-SDIO:
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*
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* D0 --- Connected to P1[6]
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* D1 --- Connected to P2[11]
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* D2 --- Connected to P2[12]
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* D3 --- Connected to P2[13]
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* CLK --- Connected to P1[2]
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* CMD --- Connected to P1[3]
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*/
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#define GPIO_SD_DAT0 GPIO_SD_DAT0_2
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#define GPIO_SD_DAT1 GPIO_SD_DAT1_2
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#define GPIO_SD_DAT2 GPIO_SD_DAT2_2
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#define GPIO_SD_DAT3 GPIO_SD_DAT3_2
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#define GPIO_SD_CLK GPIO_SD_CLK_2
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#define GPIO_SD_CMD GPIO_SD_CMD_2
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/* LCD R:
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*
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* VD0 --- Connected to P0[4]
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* VD1 --- Connected to P0[5]
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* VD2 --- Connected to P4[28]
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* VD3 --- Connected to P4[29]
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* VD4 --- Connected to P2[6]
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* VD5 --- Connected to P2[7]
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* VD6 --- Connected to P2[8]
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* VD7 --- Connected to P2[9]
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*/
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#define GPIO_LCD_VD0 GPIO_LCD_VD0_1
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#define GPIO_LCD_VD1 GPIO_LCD_VD1_1
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#define GPIO_LCD_VD2 GPIO_LCD_VD2_2
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#define GPIO_LCD_VD3 GPIO_LCD_VD3_3
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#define GPIO_LCD_VD4 GPIO_LCD_VD4_1
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#define GPIO_LCD_VD5 GPIO_LCD_VD5_1
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#define GPIO_LCD_VD6 GPIO_LCD_VD6_2
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#define GPIO_LCD_VD7 GPIO_LCD_VD7_2
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/* LCD G:
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*
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* VD8 --- Connected to P0[6]
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* VD9 --- Connected to P0[7]
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* VD10 --- Connected to P1[20]
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* VD11 --- Connected to P1[21]
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* VD12 --- Connected to P1[22]
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* VD13 --- Connected to P1[23]
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* VD14 --- Connected to P1[24]
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* VD15 --- Connected to P1[25]
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*/
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#define GPIO_LCD_VD8 GPIO_LCD_VD8_1
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#define GPIO_LCD_VD9 GPIO_LCD_VD9_1
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#define GPIO_LCD_VD10 GPIO_LCD_VD10_1
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#define GPIO_LCD_VD11 GPIO_LCD_VD11_1
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#define GPIO_LCD_VD12 GPIO_LCD_VD12_1
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#define GPIO_LCD_VD13 GPIO_LCD_VD13_1
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#define GPIO_LCD_VD14 GPIO_LCD_VD14_1
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#define GPIO_LCD_VD15 GPIO_LCD_VD15_1
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/* LCD B:
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*
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* VD16 --- Connected to P0[8]
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* VD17 --- Connected to P0[9]
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* VD18 --- Connected to P2[12]
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* VD19 --- Connected to P2[13]
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* VD20 --- Connected to P1[26]
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* VD21 --- Connected to P1[27]
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* VD22 --- Connected to P1[28]
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* VD23 --- Connected to P1[29]
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*
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* DCLK --- Connected to P2[2]
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* LP --- Connected to P2[5]
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* FP --- Connected to P2[3]
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* ENAB_M --- Connected to P2[4]
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* PWR --- Connected to P2[0]
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*/
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#define GPIO_SSP0_SCK GPIO_SSP0_SCK_3
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#define GPIO_SSP0_MISO GPIO_SSP0_MISO_2
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#define GPIO_SSP0_MOSI GPIO_SSP0_MOSI_4
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/* XPT2046 Touchscreen:
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*
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* -------------- -------------------- ------------ -------------------------
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* XTPT2046 Module Module LX_CPU LED
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* Signal Connector Connector
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* -------------- -------------------- ------------ -------------------------
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* Pin 11 PENIRQ\ PENIRQ (pulled high) PORT3 Pin 1 P2.15 PENIRQ
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* Pin 12 DOUT MISO PORT3 Pin 4 P1.18 MISO1
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* (Also USB HOST UP LED)
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* Pin 13 BUSY BUSY (pulled high) PORT3 Pin 9 P2.14 BUSY
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* Pin 14 DIN MOSI PORT3 Pin 3 P0.13 MOSI1
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* (Also USB Device up
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* LED and SD CD pin)
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* Pin 15 CS\ SSEL (pulled high) PORT3 Pin 6 P1.8 GPIO
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* (Also RMII_CRS_DV)
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* Pin 16 DCLK SCK PORT3 Pin 5 P1.19 SCK1
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* -------------- -------------------- ------------ -------------------------
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*/
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#define GPIO_SSP1_MISO GPIO_SSP1_MISO_3
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#define GPIO_SSP1_MOSI GPIO_SSP1_MOSI_2
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#define GPIO_SSP1_SCK GPIO_SSP1_SCK_2
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#define UL_DRV_SYSLESS_CHIP "16450"
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#define UL_DRV_SYSLESS_PORT LPC17_40_UART1_BASE
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#define UL_DRV_SYSLESS_BAUD 19200
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#define UL_DRV_SYSLESS_BAUDBASE ((BOARD_PCLK_FREQUENCY + 8) / 16)
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#define UL_DRV_SYSLESS_IRQ LPC17_40_IRQ_UART1
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#define UL_DRV_SYSLESS_MY_ADR_DEFAULT 3
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struct nuttx_ulan_chip_data_s
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{
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const char *chip;
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int my_adr;
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int baud;
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int baudbase;
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int irq;
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int port;
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};
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int nuttx_ulan_get_chip_data(int minor,
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struct nuttx_ulan_chip_data_s *chip_data);
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#endif /* __BOARDS_ARM_LPC17XX_40XX_LX_CPU_INCLUDE_BOARD_H */
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