375 lines
16 KiB
C
375 lines
16 KiB
C
/************************************************************************************
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* arch/arm/src/sam34/sam4l_periphclks.h
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*
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAM34_SAM4L_PERIPHCLKS_H
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#define __ARCH_ARM_SRC_SAM34_SAM4L_PERIPHCLKS_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip/sam4l_pm.h"
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#ifdef CONFIG_ARCH_CHIP_SAM4L
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* SAM4L helper macros */
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#define sam_enableperipheral(a,s) sam_modifyperipheral(a,0,s)
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#define sam_disableperipheral(a,s) sam_modifyperipheral(a,s,0)
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#define sam_cpu_enableperipheral(s) sam_enableperipheral(SAM_PM_CPUMASK,s)
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#define sam_hsb_enableperipheral(s) sam_enableperipheral(SAM_PM_HSBMASK,s)
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#define sam_pbc_enableperipheral(s) sam_enableperipheral(SAM_PM_PBCMASK,s)
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#define sam_pbd_enableperipheral(s) sam_enableperipheral(SAM_PM_PBDMASK,s)
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#define sam_cpu_disableperipheral(s) sam_disableperipheral(SAM_PM_CPUMASK,s)
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#define sam_hsb_disableperipheral(s) sam_disableperipheral(SAM_PM_HSBMASK,s)
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#define sam_pbc_enableperipheral(s) sam_enableperipheral(SAM_PM_PBCMASK,s)
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#define sam_pbd_enableperipheral(s) sam_enableperipheral(SAM_PM_PBDMASK,s)
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#define sam_pba_enabledivmask(s) sam_pba_modifydivmask(0,s)
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#define sam_pba_disabledivmask(s) sam_pba_modifydivmask(s,0)
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/* Macros to enable clocking to individual peripherals */
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#define sam_aesa_enableclk() sam_hsb_enableperipheral(PM_HSBMASK_AESA)
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#define sam_iisc_enableclk() sam_pba_enableperipheral(PM_PBAMASK_IISC)
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#define sam_spi0_enableclk() sam_pba_enableperipheral(PM_PBAMASK_SPI)
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#define sam_tc0_enableclk() \
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do { \
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sam_pba_enableperipheral(PM_PBAMASK_TC0); \
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sam_pba_enabledivmask(PM_PBADIVMASK_TIMER_CLOCKS); \
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} while (0)
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#define sam_tc1_enableclk() \
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do { \
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sam_pba_enableperipheral(PM_PBAMASK_TC1); \
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sam_pba_enabledivmask(PM_PBADIVMASK_TIMER_CLOCKS); \
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} while (0)
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#define sam_twim0_enableclk() sam_pba_enableperipheral(PM_PBAMASK_TWIM0)
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#define sam_twis0_enableclk() sam_pba_enableperipheral(PM_PBAMASK_TWIS0)
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#define sam_twim1_enableclk() sam_pba_enableperipheral(PM_PBAMASK_TWIM1)
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#define sam_twis1_enableclk() sam_pba_enableperipheral(PM_PBAMASK_TWIS1)
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#define sam_usart0_enableclk() \
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do { \
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sam_pba_enableperipheral(PM_PBAMASK_USART0); \
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sam_pba_enabledivmask(PM_PBADIVMASK_CLK_USART); \
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} while (0)
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#define sam_usart1_enableclk() \
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do { \
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sam_pba_enableperipheral(PM_PBAMASK_USART1); \
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sam_pba_enabledivmask(PM_PBADIVMASK_CLK_USART); \
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} while (0)
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#define sam_usart2_enableclk() \
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do { \
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sam_pba_enableperipheral(PM_PBAMASK_USART2); \
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sam_pba_enabledivmask(PBA_DIVMASK_CLK_USART); \
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} while (0)
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#define sam_usart3_enableclk() \
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do { \
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sam_pba_enableperipheral(PM_PBAMASK_USART3); \
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sam_pba_enabledivmask(PBA_DIVMASK_CLK_USART); \
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} while (0)
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#define sam_adcife_enableclk() sam_pba_enableperipheral(PM_PBAMASK_ADCIFE)
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#define sam_dacc_enableclk() sam_pba_enableperipheral(PM_PBAMASK_DACC)
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#define sam_acifc_enableclk() sam_pba_enableperipheral(PM_PBAMASK_ACIFC)
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#define sam_gloc_enableclk() sam_pba_enableperipheral(PM_PBAMASK_GLOC)
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#define sam_abdacb_enableclk() sam_pba_enableperipheral(PM_PBAMASK_ABDACB)
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#define sam_trng_enableclk() sam_pba_enableperipheral(PM_PBAMASK_TRNG)
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#define sam_parc_enableclk() sam_pba_enableperipheral(PM_PBAMASK_PARC)
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#define sam_catb_enableclk() sam_pba_enableperipheral(PM_PBAMASK_CATB)
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#define sam_twim2_enableclk() sam_pba_enableperipheral(PM_PBAMASK_TWIM2)
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#define sam_twim3_enableclk() sam_pba_enableperipheral(PM_PBAMASK_TWIM3)
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#define sam_lcdca_enableclk() sam_pba_enableperipheral(PM_PBAMASK_LCDCA)
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#define sam_flashcalw_enableclk() \
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do { \
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sam_hsb_enableperipheral(PM_HSBMASK_FLASHCALW); \
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sam_pbb_enableperipheral(PM_PBBMASK_FLASHCALW); \
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} while (0)
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#define sam_picocache_enableclk() \
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do { \
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sam_hsb_enableperipheral(PM_HSBMASK_HRAMC1); \
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sam_pbb_enableperipheral(PM_PBBMASK_HRAMC1); \
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} while (0)
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#define sam_hmatrix_enableclk() sam_pbb_enableperipheral(PM_PBBMASK_HMATRIX)
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#define sam_pdca_enableclk() \
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do { \
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sam_hsb_enableperipheral(PM_HSBMASK_PDCA); \
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sam_pbb_enableperipheral(PM_PBBMASK_PDCA); \
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} while (0)
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#define sam_crccu_enableclk() \
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do { \
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sam_hsb_enableperipheral(PM_HSBMASK_CRCCU); \
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sam_pbb_enableperipheral(PM_PBBMASK_CRCCU); \
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} while (0)
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#define sam_pevc_enableclk() sam_pbb_enableperipheral(PM_PBBMASK_PEVC)
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#define sam_pm_enableclk() sam_pbc_enableperipheral(PM_PBCMASK_PM)
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#define sam_chipid_enableclk() sam_pbc_enableperipheral(PM_PBCMASK_CHIPID)
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#define sam_scif_enableclk() sam_pbc_enableperipheral(PM_PBCMASK_SCIF)
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#define sam_freqm_enableclk() sam_pbc_enableperipheral(PM_PBCMASK_FREQM)
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#define sam_gpio_enableclk() sam_pbc_enableperipheral(PM_PBCMASK_GPIO)
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#define sam_bpm_enableclk() sam_pbd_enableperipheral(PM_PBDMASK_BPM)
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#define sam_bscif_enableclk() sam_pbd_enableperipheral(PM_PBDMASK_BSCIF)
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#define sam_ast_enableclk() sam_pbd_enableperipheral(PM_PBDMASK_AST)
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#define sam_wdt_enableclk() sam_pbd_enableperipheral(PM_PBDMASK_WDT)
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#define sam_eic_enableclk() sam_pbd_enableperipheral(PM_PBDMASK_EIC)
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#define sam_picouart_enableclk() sam_pbd_enableperipheral(PM_PBDMASK_PICOUART)
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/* Macros to disable clocking to individual peripherals */
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#define sam_aesa_disableclk() sam_hsb_disableperipheral(PM_HSBMASK_AESA)
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#define sam_iisc_disableclk() sam_pba_disableperipheral(PM_PBAMASK_IISC)
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#define sam_spi0_disableclk() sam_pba_disableperipheral(PM_PBAMASK_SPI)
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#define sam_tc0_disableclk() sam_pba_disableperipheral(PM_PBAMASK_TC0)
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#define sam_tc1_disableclk() sam_pba_disableperipheral(PM_PBAMASK_TC1)
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#define sam_twim0_disableclk() sam_pba_disableperipheral(PM_PBAMASK_TWIM0)
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#define sam_twis0_disableclk() sam_pba_disableperipheral(PM_PBAMASK_TWIS0)
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#define sam_twim1_disableclk() sam_pba_disableperipheral(PM_PBAMASK_TWIM1)
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#define sam_twis1_disableclk() sam_pba_disableperipheral(PM_PBAMASK_TWIS1)
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#define sam_usart0_disableclk() sam_pba_disableperipheral(PM_PBAMASK_USART0)
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#define sam_usart1_disableclk() sam_pba_disableperipheral(PM_PBAMASK_USART1)
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#define sam_usart2_disableclk() sam_pba_disableperipheral(PM_PBAMASK_USART2)
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#define sam_usart3_disableclk() sam_pba_disableperipheral(PM_PBAMASK_USART3)
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#define sam_adcife_disableclk() sam_pba_disableperipheral(PM_PBAMASK_ADCIFE)
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#define sam_dacc_disableclk() sam_pba_disableperipheral(PM_PBAMASK_DACC)
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#define sam_acifc_disableclk() sam_pba_disableperipheral(PM_PBAMASK_ACIFC)
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#define sam_gloc_disableclk() sam_pba_disableperipheral(PM_PBAMASK_GLOC)
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#define sam_abdacb_disableclk() sam_pba_disableperipheral(PM_PBAMASK_ABDACB)
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#define sam_trng_disableclk() sam_pba_disableperipheral(PM_PBAMASK_TRNG)
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#define sam_parc_disableclk() sam_pba_disableperipheral(PM_PBAMASK_PARC)
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#define sam_catb_disableclk() sam_pba_disableperipheral(PM_PBAMASK_CATB)
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#define sam_twim2_disableclk() sam_pba_disableperipheral(PM_PBAMASK_TWIM2)
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#define sam_twim3_disableclk() sam_pba_disableperipheral(PM_PBAMASK_TWIM3)
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#define sam_lcdca_disableclk() sam_pba_disableperipheral(PM_PBAMASK_LCDCA)
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#define sam_flashcalw_disableclk() sam_pba_disableperipheral(PM_HSBMASK_FLASHCALW)
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#define sam_picocache_disableclk() \
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do { \
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sam_hsb_disableperipheral(PM_HSBMASK_HRAMC1); \
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sam_pbb_disableperipheral(PM_PBBMASK_HRAMC1); \
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} while (0)
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#define sam_hmatrix_disableclk() sam_pbb_disableperipheral(PM_PBBMASK_HMATRIX)
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#define sam_pdca_disableclk() \
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do { \
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sam_hsb_disableperipheral(PM_HSBMASK_PDCA); \
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sam_pbb_disableperipheral(PM_PBBMASK_PDCA); \
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} while (0)
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#define sam_crccu_disableclk() \
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do { \
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sam_hsb_disableperipheral(PM_HSBMASK_CRCCU); \
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sam_pbb_disableperipheral(PM_PBBMASK_CRCCU); \
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} while (0)
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#define sam_pevc_disableclk() sam_pbb_disableperipheral(PM_PBBMASK_PEVC)
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#define sam_pm_disableclk() sam_pbc_disableperipheral(PM_PBCMASK_PM)
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#define sam_chipid_disableclk() sam_pbc_disableperipheral(PM_PBCMASK_CHIPID)
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#define sam_scif_disableclk() sam_pbc_disableperipheral(PM_PBCMASK_SCIF)
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#define sam_freqm_disableclk() sam_pbc_disableperipheral(PM_PBCMASK_FREQM)
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#define sam_gpio_disableclk() sam_pbc_disableperipheral(PM_PBCMASK_GPIO)
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#define sam_bpm_disableclk() sam_pbd_disableperipheral(PM_PBDMASK_BPM)
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#define sam_bscif_disableclk() sam_pbd_disableperipheral(PM_PBDMASK_BSCIF)
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#define sam_ast_disableclk() sam_pbd_disableperipheral(PM_PBDMASK_AST)
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#define sam_wdt_disableclk() sam_pbd_disableperipheral(PM_PBDMASK_WDT)
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#define sam_eic_disableclk() sam_pbd_disableperipheral(PM_PBDMASK_EIC)
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#define sam_picouart_disableclk() sam_pbd_disableperipheral(PM_PBDMASK_PICOUART)
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Inline Functions
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************************************************************************************/
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#ifndef __ASSEMBLY__
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/************************************************************************************
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* Public Data
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************************************************************************************/
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#undef EXTERN
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#if defined(__cplusplus)
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/************************************************************************************
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* Public Function Prototypes
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************************************************************************************/
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/************************************************************************************
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* Name: sam_init_periphclks
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*
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* Description:
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* Called during boot to enable clocking on all selected peripherals.
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*
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************************************************************************************/
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void sam_init_periphclks(void);
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/************************************************************************************
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* Name: sam_modifyperipheral
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*
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* Description:
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* This is a convenience function that is intended to be used to enable or disable
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* module clocking.
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*
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************************************************************************************/
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void sam_modifyperipheral(uintptr_t regaddr, uint32_t clrbits, uint32_t setbits);
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/************************************************************************************
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* Name: sam_pba_modifydivmask
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*
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* Description:
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* This is a convenience function that is intended to be used to modify bits in
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* the PBA divided clock (DIVMASK) register.
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*
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************************************************************************************/
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void sam_pba_modifydivmask(uint32_t clrbits, uint32_t setbits);
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/************************************************************************************
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* Name: sam_pba_enableperipheral
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*
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* Description:
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* This is a convenience function to enable a peripheral on the APBA bridge.
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*
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************************************************************************************/
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void sam_pba_enableperipheral(uint32_t bitset);
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/************************************************************************************
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* Name: sam_pba_disableperipheral
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*
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* Description:
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* This is a convenience function to disable a peripheral on the APBA bridge.
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*
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************************************************************************************/
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void sam_pba_disableperipheral(uint32_t bitset);
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/************************************************************************************
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* Name: sam_pbb_enableperipheral
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*
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* Description:
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* This is a convenience function to enable a peripheral on the APBB bridge.
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*
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************************************************************************************/
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void sam_pbb_enableperipheral(uint32_t bitset);
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/************************************************************************************
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* Name: sam_pbb_disableperipheral
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*
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* Description:
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* This is a convenience function to disable a peripheral on the APBA bridge.
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*
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************************************************************************************/
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void sam_pbb_disableperipheral(uint32_t bitset);
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/************************************************************************************
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* Name: sam_usbc_enableclk
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*
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* Description:
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* Enable clocking for the USBC using settings from the board.h header files.
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*
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* "The USBC has two bus clocks connected: One High Speed Bus clock
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* (CLK_USBC_AHB) and one Peripheral Bus clock (CLK_USBC_APB). These clocks
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* are generated by the Power Manager. Both clocks are enabled at reset
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* and can be disabled by the Power Manager. It is recommended to disable
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* the USBC before disabling the clocks, to avoid freezing the USBC in
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* an undefined state.
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*
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* "To follow the usb data rate at 12Mbit/s in full-speed mode, the
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* CLK_USBC_AHB clock should be at minimum 12MHz.
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*
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* "The 48MHz USB clock is generated by a dedicated generic clock from
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* the SCIF module. Before using the USB, the user must ensure that the
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* USB generic clock (GCLK_USBC) is enabled at 48MHz in the SCIF module."
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*
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************************************************************************************/
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#ifdef CONFIG_SAM34_USBC
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void sam_usbc_enableclk(void);
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#endif
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/************************************************************************************
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* Name: sam_usbc_disableclk
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*
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* Description:
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* Disable clocking to the USBC.
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*
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************************************************************************************/
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#ifdef CONFIG_SAM34_USBC
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void sam_usbc_disableclk(void);
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#endif
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#undef EXTERN
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#if defined(__cplusplus)
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* CONFIG_ARCH_CHIP_SAM4L */
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#endif /* __ARCH_ARM_SRC_SAM34_SAM4L_PERIPHCLKS_H */
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