24e45d071e
Pinephone Pro port just nsh Status: booting till GICD / IRQ issue style cleanups start to fix style checks revert offset whitespaces revert a64 bringup file prob last cleanup more cleanups remove dts move changes from a64 hardware specific folders to rk3399 undo common changes (except head.s) revert gitignore missing irq.h and rk3399_serial.c need to finish cleaning them up WIP add source for load address make debug print hex again add board include Pinephone Pro port just nsh Status: booting till GICD / IRQ issue style cleanups start to fix style checks revert offset whitespaces revert a64 bringup file prob last cleanup more cleanups remove dts move changes from a64 hardware specific folders to rk3399 undo common changes (except head.s) revert gitignore missing irq.h and rk3399_serial.c need to finish cleaning them up WIP add source for load address remove ccache, add board memory map remove board reset
282 lines
6.7 KiB
Plaintext
282 lines
6.7 KiB
Plaintext
#
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# For a description of the syntax of this configuration file,
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# see the file kconfig-language.txt in the NuttX tools repository.
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#
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if ARCH_ARM64
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comment "ARM64 Options"
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choice
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prompt "ARM64 Toolchain Selection"
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default ARM64_TOOLCHAIN_GNU_EABI
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config ARM64_TOOLCHAIN_GNU_EABI
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bool "Generic GNU EABI toolchain"
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select ARCH_TOOLCHAIN_GNU
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---help---
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This option should work for any modern GNU toolchain (GCC 4.5 or newer)
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config ARM64_TOOLCHAIN_CLANG
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bool "LLVM Clang toolchain"
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select ARCH_TOOLCHAIN_CLANG
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endchoice
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choice
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prompt "ARM64 chip selection"
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default ARCH_CHIP_QEMU
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config ARCH_CHIP_A64
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bool "Allwinner A64"
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select ARCH_CORTEX_A53
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select ARCH_HAVE_ADDRENV
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select ARCH_HAVE_RESET
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select ARCH_HAVE_PSCI
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select ARCH_NEED_ADDRENV_MAPPING
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---help---
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Allwinner A64 SoC
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config ARCH_CHIP_RK3399
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bool "Rockchip RK3399"
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select ARCH_CORTEX_A53
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select ARCH_HAVE_ADDRENV
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select ARCH_HAVE_RESET
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select ARCH_HAVE_PSCI
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select ARCH_NEED_ADDRENV_MAPPING
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---help---
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Rockchip RK3399 SoC
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config ARCH_CHIP_QEMU
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bool "QEMU virt platform (ARMv8a)"
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select ARCH_HAVE_ADDRENV
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select ARCH_NEED_ADDRENV_MAPPING
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---help---
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QEMU virt platform (ARMv8a)
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config ARCH_CHIP_FVP_ARMV8R
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bool "ARM FVP virt platform (ARMv8r)"
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select ARCH_CORTEX_R82
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---help---
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ARM FVP virt platform (ARMv8r)
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config ARCH_CHIP_IMX8
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bool "NXP i.MX8 Platform (ARMv8a)"
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select ARCH_HAVE_ADDRENV
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select ARCH_HAVE_IRQTRIGGER
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select ARCH_NEED_ADDRENV_MAPPING
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---help---
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NXP i.MX8 (ARMv8a) applications processors
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config ARCH_CHIP_ARM64_CUSTOM
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bool "Custom ARM64 chip"
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select ARCH_CHIP_CUSTOM
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---help---
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Select this option if there is no directory for the chip under arch/arm64/src/.
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endchoice
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config ARCH_ARMV8A
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bool
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default n
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select ARCH_HAVE_EL3
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config ARCH_ARMV8R
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bool
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default n
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select ARCH_SINGLE_SECURITY_STATE
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config ARCH_HAVE_PSCI
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bool "ARM PCSI (Power State Coordination Interface) Support"
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default n
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---help---
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This Power State Coordination Interface (PSCI) defines
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a standard interface for power management. the PCSI need
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to implement handling firmware at EL2 or EL3. The option
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maybe not applicable for arm core without PCSI firmware
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interface implement
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config ARCH_SINGLE_SECURITY_STATE
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bool "ARM Single Security State Support"
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default n
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---help---
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Some ARM aarch64 Cortex-family processors only supports single
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security state(eg. Cortex-R82). For these Processors,
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GIC or other ARM architecture feature will with different
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configure
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config ARCH_HAVE_EL3
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bool
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default n
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---help---
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Some ARM aarch64 Cortex-family processors only supports
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EL0~El2(eg. Cortex-R82). For these Processors, the code
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runing at EL3 is not necessary and system register for EL3
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is not accessible
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config ARCH_SET_VMPIDR_EL2
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bool "Set VMPIDR_EL2 at EL2 stage"
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---help---
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VMPIDR_EL2 holds the value of the Virtualization Multiprocessor ID.
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From architecture manual of AArch64, the behave is:
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-reading register MPIDR_EL1 in EL2, it's return real MPIDR_EL1
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-reading register MPIDR_EL1 in EL1, it's return VMPIDR_EL2
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So since NuttX for SMP is running at EL1 to read MPIDR_EL1 for
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identify CPU id, it's need to set VMPIDR_EL2 to MPIDR_EL1 for
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every CPU at boot EL2 stage.
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For some platform, the bootloader or hypervisor will do that at
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the EL2 stage, but not all.
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ARM FVP and VDK should set it since these platform will boot
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without BootLoader.
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config ARCH_EARLY_PRINT
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bool "arch early print support"
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default n
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---help---
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The aarch64 have EL0~El3 execute level and NS/S (security state),
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the NuttX should be execute at EL1 in NS(ARmv8-A) or S(ARmv8-R)
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state. but booting NuttX have different ELs and state while with
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different platform, if NuttX runing at wrong ELs or state it will
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not normal anymore. So we need to print something in arm64_head.S
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to debug this situation.
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Enabling this option will need to implement arm64_earlyprintinit and
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arm64_lowputc functions just you see in qemu_lowputc.S.
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by default, UART dev will be used. You can also logging the booting
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message through rewriting fake arm64_lowputc with other debug
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method (eg semihosting , ARM debug channel etc)
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if you not sure, keeping the option disable.
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config ARCH_CORTEX_A53
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bool
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default n
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select ARCH_ARMV8A
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select ARCH_HAVE_TRUSTZONE
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select ARCH_DCACHE
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select ARCH_ICACHE
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select ARCH_HAVE_MMU
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select ARCH_HAVE_FPU
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select ARCH_HAVE_TESTSET
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select ARM_HAVE_NEON
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config ARCH_CORTEX_A57
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bool
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default n
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select ARCH_ARMV8A
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select ARCH_HAVE_TRUSTZONE
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select ARCH_DCACHE
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select ARCH_ICACHE
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select ARCH_HAVE_MMU
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select ARCH_HAVE_FPU
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select ARCH_HAVE_TESTSET
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select ARM_HAVE_NEON
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config ARCH_CORTEX_A72
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bool
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default n
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select ARCH_ARMV8A
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select ARCH_HAVE_TRUSTZONE
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select ARCH_DCACHE
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select ARCH_ICACHE
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select ARCH_HAVE_MMU
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select ARCH_HAVE_FPU
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select ARCH_HAVE_TESTSET
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select ARM_HAVE_NEON
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config ARCH_CORTEX_R82
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bool
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default n
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select ARCH_ARMV8R
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select ARCH_DCACHE
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select ARCH_ICACHE
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select ARCH_HAVE_MPU
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select ARCH_HAVE_FPU
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select ARCH_HAVE_TESTSET
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select ARM_HAVE_NEON
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config ARCH_FAMILY
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string
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default "armv8-a" if ARCH_ARMV8A
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default "armv8-r" if ARCH_ARMV8R
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config ARCH_CHIP
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string
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default "a64" if ARCH_CHIP_A64
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default "rk3399" if ARCH_CHIP_RK3399
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default "qemu" if ARCH_CHIP_QEMU
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default "fvp-v8r" if ARCH_CHIP_FVP_ARMV8R
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default "imx8" if ARCH_CHIP_IMX8
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config ARM_HAVE_NEON
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bool
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default n
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---help---
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Decide whether support NEON instruction
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config ARM_GIC_VERSION
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int "GIC version"
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default 2 if ARCH_CHIP_A64
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default 3
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range 2 4
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---help---
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Version of Generic Interrupt Controller (GIC) supported by the
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architecture
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if ARM_GIC_VERSION = 2
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config ARM_GIC_EOIMODE
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bool
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default n
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---help---
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Enable GICC_CTLR.EOImode, this will separates the priority drop and interrupt
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deactivation operations.
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endif
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config ARM64_SEMIHOSTING_HOSTFS
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bool "Semihosting HostFS"
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depends on FS_HOSTFS
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---help---
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Mount HostFS through semihosting.
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This doesn't support some directory operations like readdir because
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of the limitations of semihosting mechanism.
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if ARM64_SEMIHOSTING_HOSTFS
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config ARM64_SEMIHOSTING_HOSTFS_CACHE_COHERENCE
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bool "Cache coherence in semihosting hostfs"
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depends on ARCH_DCACHE
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---help---
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Flush & Invalidte cache before & after bkpt instruction.
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endif
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config ARM64_DCACHE_DISABLE
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bool "Disable DCACHE at __start"
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default n
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config ARM64_ICACHE_DISABLE
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bool "Disable ICACHE at __start"
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default n
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if ARCH_CHIP_A64
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source "arch/arm64/src/a64/Kconfig"
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endif
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if ARCH_CHIP_RK3399
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source "arch/arm64/src/rk3399/Kconfig"
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endif
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if ARCH_CHIP_QEMU
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source "arch/arm64/src/qemu/Kconfig"
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endif
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if ARCH_CHIP_FVP_ARMV8R
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source "arch/arm64/src/fvp-v8r/Kconfig"
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endif
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if ARCH_CHIP_IMX8
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source "arch/arm64/src/imx8/Kconfig"
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endif
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endif # ARCH_ARM64
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