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The Inter-Processor Interrupt that pauses the other CPU generates a level-1 interrupt which sets the PS.EXCM. This level-1 interrupt is treated as an Exception and the bit PS.EXCM bit is automatically reset on return from Exception. However, this is not the case here because we are changing the execution to the signal trampoline. Restoring the PS register with the PS.EXCM bit set would cause any other exception to deviate execution to the DEC (double exception vector), avoiding it to be treated correctly. According to the xtensa ISA: "The process of taking an interrupt does not clear the interrupt request. The process does set PS.EXCM to 1, which disables level-1 interrupts in the interrupt handler. Typically, the PS.EXCM is reset to 0 by the handler, after it has set up the stack frame and masked the interrupt." Clean the saved PS.EXCM to 1) avoid an exception from being properly treated and 2) avoid interrupts to be masked while delivering the signal. |
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