f8aed9864d
Max Holtzberg has submitted the ICLA and we can migrate the licenses to Apache. Gregory Nutt has submitted the SGA and we can migrate the licenses to Apache. Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
63 lines
2.8 KiB
C
63 lines
2.8 KiB
C
/****************************************************************************
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* arch/arm/src/stm32/hardware/stm32_rng.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RNG_H
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#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RNG_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Register Offsets *********************************************************/
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#define STM32_RNG_CR_OFFSET 0x0000 /* RNG Control Register */
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#define STM32_RNG_SR_OFFSET 0x0004 /* RNG Status Register */
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#define STM32_RNG_DR_OFFSET 0x0008 /* RNG Data Register */
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/* Register Addresses *******************************************************/
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#define STM32_RNG_CR (STM32_RNG_BASE+STM32_RNG_CR_OFFSET)
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#define STM32_RNG_SR (STM32_RNG_BASE+STM32_RNG_SR_OFFSET)
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#define STM32_RNG_DR (STM32_RNG_BASE+STM32_RNG_DR_OFFSET)
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/* Register Bitfield Definitions ********************************************/
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/* RNG Control Register */
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#define RNG_CR_RNGEN (1 << 2) /* Bit 2: RNG enable */
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#define RNG_CR_IE (1 << 3) /* Bit 3: Interrupt enable */
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/* RNG Status Register */
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#define RNG_SR_DRDY (1 << 0) /* Bit 0: Data ready */
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#define RNG_SR_CECS (1 << 1) /* Bit 1: Clock error current status */
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#define RNG_SR_SECS (1 << 2) /* Bit 2: Seed error current status */
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#define RNG_SR_CEIS (1 << 5) /* Bit 5: Clock error interrupt status */
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#define RNG_SR_SEIS (1 << 6) /* Bit 6: Seed error interrupt status */
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#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RNG_H */
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