Henry Rovner 63375bf9cd BL808: Replace courier with M0 interrupt controller ... It turns out that the D0 core of the BL808 has an IRQ that represents all interrupt sources for the M0 core. This change uses this IRQ to access these sources, eliminating the need for IPC between M0 and D0.		2024-06-28 17:23:02 +08:00
..
bl602
bl808	BL808: Replace courier with M0 interrupt controller	2024-06-28 17:23:02 +08:00
c906
esp32c3	risc-v/espressif: Rename espressif/esp32c3 as esp32c3	2024-01-30 08:32:05 +01:00
esp32c3-legacy	risc-v/esp32c3: Rename legacy approach esp32c3 as esp32c3-legacy	2024-01-30 08:32:05 +01:00
esp32c6	risc-v/espressif: Rename espressif/esp32c3 as esp32c3	2024-01-30 08:32:05 +01:00
esp32h2	risc-v/espressif: Rename espressif/esp32c3 as esp32c3	2024-01-30 08:32:05 +01:00
fe310
hpm6000	Add support for hpm6360evk	2024-02-18 09:17:56 -08:00
hpm6750
jh7110
k210
k230	risc-v/k230: add IPI support to speed up RPTUN/RPMSG	2024-02-21 04:37:03 -08:00
litex	risc-v/litex: fix typo in litex/irq.h	2024-01-06 04:15:52 -08:00
mpfs
qemu-rv
rv32m1
sg2000	arch/risc-v: Add support for SOPHGO SG2000 SoC (T-Head C906)	2024-06-17 09:41:29 +08:00
thead	arch/riscv: add T-HEAD CSR mapping	2024-04-11 22:20:39 +08:00
.gitignore
arch.h	risc-v/arch.h: revising comments	2024-03-25 20:39:24 +08:00
barriers.h
csr.h	riscv: Add indirect CSRs for CLIC	2024-06-21 03:02:59 +08:00
elf.h	arch/risc-v/include/elf.f: Support coredump for rv32 and rv64 targets.	2024-06-18 10:41:56 +08:00
inttypes.h	arch/risc-v: move PRIxREG to inttypes.h	2024-06-22 22:00:06 +08:00
irq.h	riscv: Improve exception and irq mapping	2024-06-26 09:07:52 +08:00
limits.h	arch/risc-v: initial qemu-rv64ilp32 support	2024-06-14 19:50:00 +08:00
mode.h	arch/risc-v: add risc-v SSTC extension support	2024-04-27 22:09:22 -03:00
setjmp.h
spinlock.h
stdarg.h
syscall.h	riscv/syscall: Optimize user service call performance	2024-06-01 10:40:53 -03:00
types.h	arch/risc-v: Improve the SBI function handle	2024-06-19 20:55:10 +08:00