106 lines
5.2 KiB
C
106 lines
5.2 KiB
C
/****************************************************************************************
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* arch/arm/src/sam34/chip/sam_rswdt.h
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* Reinforced Safety Watchdog Timer (RSWDT) for the SAM4E
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*
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* Copyright (C) 2014 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_RSWDT_H
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#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_RSWDT_H
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/****************************************************************************************
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* Included Files
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****************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#include "chip/sam_memorymap.h"
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/****************************************************************************************
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* Pre-processor Definitions
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****************************************************************************************/
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/* RSWDT register offsets ***************************************************************/
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#define SAM_RSWDT_CR_OFFSET 0x0000 /* Control Register */
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#define SAM_RSWDT_MR_OFFSET 0x0004 /* Mode Register */
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#define SAM_RSWDT_SR_OFFSET 0x0008 /* Status Register */
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/* RSWDT register addresses *************************************************************/
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#define SAM_RSWDT_CR (SAM_RSWDT_BASE+SAM_RSWDT_CR_OFFSET)
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#define SAM_RSWDT_MR (SAM_RSWDT_BASE+SAM_RSWDT_MR_OFFSET)
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#define SAM_RSWDT_SR (SAM_RSWDT_BASE+SAM_RSWDT_SR_OFFSET)
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/* RSWDT register bit definitions *******************************************************/
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/* Watchdog Timer Control Register */
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#define RSWDT_CR_WDRSTT (1 << 0) /* Bit 0: Watchdog Rest */
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#define RSWDT_CR_KEY_SHIFT (24) /* Bits 24-31: Password */
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#define RSWDT_CR_KEY_MASK (0xff << RSWDT_CR_KEY_SHIFT)
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# define RSWDT_CR_KEY (0xc4 << RSWDT_CR_KEY_SHIFT)
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/* Watchdog Timer Mode Register */
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#define RSWDT_MR_WDV_SHIFT (0) /* Bits 0-11: Watchdog Counter Value */
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#define RSWDT_MR_WDV_MASK (0xfff << RSWDT_MR_WDV_SHIFT)
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# define RSWDT_MR_WDV(n) ((uint32_t)(n) << RSWDT_MR_WDV_SHIFT)
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#define RSWDT_MR_WDFIEN (1 << 12) /* Bit 12: Watchdog Fault Interrupt Enable */
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#define RSWDT_MR_WDRSTEN (1 << 13) /* Bit 13: Watchdog Reset Enable */
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#define RSWDT_MR_WDRPROC (1 << 14) /* Bit 14: Watchdog Reset Processor */
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#define RSWDT_MR_WDDIS (1 << 15) /* Bit 15: Watchdog Disable */
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#define RSWDT_MR_WDD_SHIFT (16) /* Bits 16-27: Watchdog Delta Value */
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#define RSWDT_MR_WDD_MASK (0xfff << RSWDT_MR_WDD_SHIFT)
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# define RSWDT_MR_WDD(n) ((uint32_t)(n) << RSWDT_MR_WDD_SHIFT)
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#define RSWDT_MR_WDDBGHLT (1 << 28) /* Bit 28: Watchdog Debug Halt */
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#define RSWDT_MR_WDIDLEHLT (1 << 29) /* Bit 29: Watchdog Idle Halt */
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/* Watchdog Timer Status Register */
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#define RSWDT_SR_WDUNF (1 << 0) /* Bit 0: Watchdog Underflow */
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#define RSWDT_SR_WDERR (1 << 1) /* Bit 1: Watchdog Error */
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/****************************************************************************************
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* Public Types
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****************************************************************************************/
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/****************************************************************************************
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* Public Data
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****************************************************************************************/
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/****************************************************************************************
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* Public Functions
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****************************************************************************************/
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#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_RSWDT_H */
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