Huang Qi 898d789a5f arch/risc-v/riscv_misaligned: Correct sw source register ... If source register of sw instruction is x0, we must point it to a constant zero since in NuttX's context, value of index 0 is EPC. Signed-off-by: Huang Qi <huangqi3@xiaomi.com>		2022-04-13 18:33:36 +08:00
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bl602	arch/risc-v: Apply misaligned access handler for k210/bl602	2022-04-13 01:10:49 +08:00
c906	risc-v/c906: fix build break	2022-04-12 15:49:52 +03:00
common	arch/risc-v/riscv_misaligned: Correct sw source register	2022-04-13 18:33:36 +08:00
esp32c3	RISC-V: Remove riscv_cpuindex.c from platforms that don't need it	2022-04-12 01:59:35 +08:00
fe310	arch/risc-v: Apply common mtime driver to mtime based chps	2022-04-12 12:14:40 +03:00
k210	RISC-V: Move mhartid to own assembly macro+function	2022-04-13 12:00:40 +02:00
litex	RISC-V: Remove riscv_cpuindex.c from platforms that don't need it	2022-04-12 01:59:35 +08:00
mpfs	RISC-V: Move mhartid to own assembly macro+function	2022-04-13 12:00:40 +02:00
opensbi	arch/risc-v: Update opensbi to 4998a712b2ab504eff306110879ee05af6050177	2022-03-10 19:46:01 +02:00
qemu-rv	RISC-V: Move mhartid to own assembly macro+function	2022-04-13 12:00:40 +02:00
rv32m1	RISC-V: Remove riscv_cpuindex.c from platforms that don't need it	2022-04-12 01:59:35 +08:00
.gitignore	build: Remve the unnecessary .gitignore	2020-05-23 18:00:40 +01:00
Makefile	RISC-V: Implement option to run NuttX in supervisor mode (S-mode)	2022-04-01 16:19:42 -03:00