d42fc094fa
arm: stm32: codestyle fixes
* arm: stm32f0l0g0: codestyle fixes
After the board restructuration is time for codestyle cleanup
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arm: stm32f7: codestyle fixes
After the board restructuration is time for codestyle cleanup
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arm: stm32h7: codestyle fixes
After the board restructuration is time for codestyle cleanup
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arm: stm32l4: codestyle fixes
After the board restructuration is time for codestyle cleanup
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arm: stm32: codestyle fixes
After the board restructuration is time for codestyle cleanup
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
276 lines
9.6 KiB
C
276 lines
9.6 KiB
C
/****************************************************************************
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* boards/arm/stm32/axoloti/include/board.h
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*
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* Copyright (C) 2019 Gregory Nutt. All rights reserved.
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* Author: Jason T. Harris <sirmanlypowers@gmail.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#ifndef __BOARDS_ARM_STM32_AXOLOTI_INCLUDE_BOARD_H
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#define __BOARDS_ARM_STM32_AXOLOTI_INCLUDE_BOARD_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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# include <stdbool.h>
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/****************************************************************************
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* Clocking
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* The Axoloti board has an external 8MHz crystal.
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* The SoC can run at 180MHz, but the required USB clock of 48MHz cannot be
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* configured at that system clock rate, so the core clock is 168MHz.
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*
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* This is the canonical configuration:
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* System Clock source : PLL (HSE)
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* SYSCLK(Hz) : 168000000 Determined by PLL configuration
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* HCLK(Hz) : 168000000 (STM32_RCC_CFGR_HPRE)
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* AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE)
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* APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1)
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* APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2)
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* HSE Frequency(Hz) : 8000000 (STM32_BOARD_XTAL)
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* PLLM : 8 (STM32_PLLCFG_PLLM)
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* PLLN : 336 (STM32_PLLCFG_PLLN)
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* PLLP : 2 (STM32_PLLCFG_PLLP)
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* PLLQ : 7 (STM32_PLLCFG_PLLQ)
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* Main regulator output voltage : Scale1 mode Needed for high speed SYSCLK
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* Flash Latency(WS) : 5
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* Prefetch Buffer : OFF
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* Instruction cache : ON
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* Data cache : ON
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* Require 48MHz for USB OTG FS, : Enabled
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* SDIO and RNG clock
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*/
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/* HSI - 16 MHz RC factory-trimmed
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* LSI - 32 KHz RC
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* HSE - On-board crystal frequency is 8MHz
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* LSE - 32.768 kHz
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*/
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#define STM32_BOARD_XTAL 8000000ul
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#define STM32_HSI_FREQUENCY 16000000ul
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#define STM32_LSI_FREQUENCY 32000
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#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
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#define STM32_LSE_FREQUENCY 32768
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/* Main PLL Configuration.
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*
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* PLL source is HSE
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* PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN
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* = (8,000,000 / 8) * 336
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* = 336,000,000
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* SYSCLK = PLL_VCO / PLLP
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* = 336,000,000 / 2 = 168,000,000
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* USB OTG FS, SDIO and RNG Clock
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* = PLL_VCO / PLLQ
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* = 48,000,000
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*/
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#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8)
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#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336)
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#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2
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#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7)
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#define STM32_SYSCLK_FREQUENCY 168000000ul
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/* AHB clock (HCLK) is SYSCLK (168MHz) */
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#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
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#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
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#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
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/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */
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#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */
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#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4)
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/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */
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#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */
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#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2)
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/****************************************************************************
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* LED Definitions
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* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any
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* way. The following definitions are used to access individual LEDs.
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*/
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/* LED index values for use with board_userled() */
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#define BOARD_LED1 0
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#define BOARD_LED2 1
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#define BOARD_NLEDS 2
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#define BOARD_LED_GREEN BOARD_LED1
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#define BOARD_LED_RED BOARD_LED2
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/* LED bits for use with board_userled_all() */
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#define BOARD_LED1_BIT (1 << BOARD_LED1)
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#define BOARD_LED2_BIT (1 << BOARD_LED2)
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/****************************************************************************
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* Button Definitions
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* There are two buttons on the axoloti, one of them is GPIO connected. The other
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* is a reset button and is not under software control.
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*/
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#define BUTTON_USER 0
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#define NUM_BUTTONS 1
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#define BUTTON_USER_BIT (1 << BUTTON_USER)
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/****************************************************************************
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* UARTs
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* The MIDI in/out ports of the axoloti are connected on USART6.
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* It maybe convenient to run a serial port connected to the header pins,
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* so we can optionally use USART1 for that.
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*/
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/* USART1 - console on header pins */
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#define GPIO_USART1_RX GPIO_USART1_RX_2 /* AF7, PB7 */
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#define GPIO_USART1_TX GPIO_USART1_TX_2 /* AF7, PB6 */
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/* USART6 - midi in/out */
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#define GPIO_USART6_RX (GPIO_ALT|GPIO_AF8|GPIO_PORTG|GPIO_PIN9| \
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GPIO_PULLUP|GPIO_SPEED_2MHz|GPIO_PUSHPULL)
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#define GPIO_USART6_TX (GPIO_ALT|GPIO_AF8|GPIO_PORTG|GPIO_PIN14| \
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GPIO_FLOAT|GPIO_SPEED_2MHz|GPIO_OPENDRAIN)
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/****************************************************************************
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* I2C Bus
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* Turn on the internal pullups since there are no external pullups.
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*/
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/* I2C1 - for external devices */
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#define GPIO_I2C1_SCL (GPIO_ALT|GPIO_AF4|GPIO_PORTB|GPIO_PIN8| \
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GPIO_SPEED_2MHz|GPIO_OPENDRAIN|GPIO_PULLUP)
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#define GPIO_I2C1_SDA (GPIO_ALT|GPIO_AF4|GPIO_PORTB|GPIO_PIN9| \
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GPIO_SPEED_2MHz|GPIO_OPENDRAIN|GPIO_PULLUP)
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/* I2C3 - for the ADAU1961 codec */
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#define GPIO_I2C3_SCL (GPIO_ALT|GPIO_AF4|GPIO_PORTH|GPIO_PIN7| \
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GPIO_SPEED_2MHz|GPIO_OPENDRAIN|GPIO_PULLUP)
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#define GPIO_I2C3_SDA (GPIO_ALT|GPIO_AF4|GPIO_PORTH|GPIO_PIN8| \
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GPIO_SPEED_2MHz|GPIO_OPENDRAIN|GPIO_PULLUP)
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/****************************************************************************
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* SAI Bus
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* Used with the ADAU1961 CODEC
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* PE3_SAI1_SD_B (GPIO_SAI1_SD_B_1)
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* PE4_SAI1_FS_A (GPIO_SAI1_FS_A)
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* PE5_SAI1_SCK_A (GPIO_SAI1_SCK_A)
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* PE6_SAI1_SD_A (GPIO_SAI1_SD_A_2)
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* PA8_MCO1
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*/
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#define GPIO_SAI1_SD_B GPIO_SAI1_SD_B_1 /* AF6, PE3 */
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#define GPIO_SAI1_SD_A GPIO_SAI1_SD_A_2 /* AF6, PE6 */
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#define STM32_SAI1_FREQUENCY (48000 * 2 * 256) /* TODO ?? */
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/* DAC DMA to Codec
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* dma 2, stream 1, channel 0
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* memory to peripheral
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* 32 bits
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*/
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#define DMACHAN_SAI1_A DMAMAP_SAI1_A_1
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/* ADC DMA from Codec
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* dma 2, stream 4, channel 1,
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* peripheral to memory
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* 32 bits
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*/
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#define DMACHAN_SAI1_B DMAMAP_SAI1_B_2
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/****************************************************************************
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* SDIO
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* Used for the SD card interface.
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* d0 (AF12, PC8)
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* d1 (AF12, PC9)
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* d2 (AF12, PC10)
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* d3 (AF12, PC11)
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* clk (AF12, PC12)
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* cmd (AF12, PD2)
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* cd1 PD13
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*/
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/* SDIO dividers. Note that slower clocking is required when DMA is disabled
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* in order to avoid RX overrun/TX underrun errors due to delayed responses
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* to service FIFOs in interrupt driven mode. These values have not been
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* tuned!!!
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*
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* SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz
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*/
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#define SDIO_INIT_CLKDIV (118 << SDIO_CLKCR_CLKDIV_SHIFT)
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/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz
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* DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz
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*/
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#ifdef CONFIG_SDIO_DMA
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# define SDIO_MMCXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT)
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#else
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# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT)
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#endif
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/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz
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* DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz
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*/
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#ifdef CONFIG_SDIO_DMA
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# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT)
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#else
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# define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT)
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#endif
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/* dma 2, stream 6, channel 4 */
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#define DMAMAP_SDIO DMAMAP_SDIO_2
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#endif /* __BOARDS_ARM_STM32_AXOLOTI_INCLUDE_BOARD_H */
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