037c9ea0a4
Summary The naming standard at https://cwiki.apache.org/confluence/display/NUTTX/Naming+FAQ requires that all MCU-private files begin with the name of the architecture, not up_. This PR addresses only these name changes for the up_*.h files. There are only three, but almost 1680 files that include them: up_arch.h up_internal.h up_vfork.h The only change to the files is from including up_arch.h to arm_arch.h (for example). The entire job required to be compatible with that Naming Convention will also require changing the naming of the up_() functions that are used only within arch/arm and board/arm. Impact There should be not impact of this change (other that one step toward more consistent naming). Testing stm32f4discovery:netnsh
155 lines
5.3 KiB
C
155 lines
5.3 KiB
C
/****************************************************************************
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* arch/arm/src/sama5/sam_timerisr.c
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*
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* Copyright (C) 2013, 2017 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <time.h>
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#include <nuttx/arch.h>
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#include <arch/irq.h>
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#include <arch/board/board.h>
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#include "arm_arch.h"
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#include "sam_periphclks.h"
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#include "hardware/sam_pit.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* The PIT counter runs at a rate of the main clock (MCK) divided by 16.
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*
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* On the SAMA5D4, the clocking to the PIC may be divided down from MCK.
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* Perhaps because of H32MXDIV? We will let the board.h tell us the correct
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* PIT include clock by defining BOARD_PIT_FREQUENCY.
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*/
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#define PIT_CLOCK (BOARD_PIT_FREQUENCY >> 4)
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/* The desired timer interrupt frequency is provided by the definition
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* CLK_TCK (see include/time.h). CLK_TCK defines the desired number of
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* system clock ticks per second. That value is a user configurable setting
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* that defaults to 100 (100 ticks per second = 10 MS interval).
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*
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* The PIT counts from zero and up until it reaches the overflow value set
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* in the field PIV of the Mode Register (PIT MR). So an PIV value of n
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* corresponds a duration of n * PIT_CLOCK
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*/
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#define PIT_PIV ((PIT_CLOCK + (CLK_TCK >> 1)) / CLK_TCK)
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Function: sam_timerisr
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*
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* Description:
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* The timer ISR will perform a variety of services for various portions
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* of the systems.
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*
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****************************************************************************/
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static int sam_timerisr(int irq, uint32_t *regs, void *arg)
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{
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/* "When CPIV and PICNT values are obtained by reading the Periodic
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* Interval Value Register (PIT_PIVR), the overflow counter (PICNT) is
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* reset and the PITS is cleared, thus acknowledging the interrupt. The
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* value of PICNT gives the number of periodic intervals elapsed since the
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* last read of PIT_PIVR."
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*/
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uint32_t picnt = getreg32(SAM_PIT_PIVR) >> PIT_PICNT_SHIFT;
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/* Process timer interrupt (multiple times if we missed an interrupt) */
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while (picnt-- > 0)
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{
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nxsched_process_timer();
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}
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return OK;
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Function: up_timer_initialize
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*
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* Description:
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* This function is called during start-up to initialize
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* the timer interrupt.
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*
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****************************************************************************/
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void up_timer_initialize(void)
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{
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uint32_t regval;
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/* Enable the PIT peripheral */
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sam_pit_enableclk();
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/* Make sure that interrupts from the PIT are disabled */
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up_disable_irq(SAM_IRQ_PIT);
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/* Attach the timer interrupt vector */
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irq_attach(SAM_IRQ_PIT, (xcpt_t)sam_timerisr, NULL);
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/* Set the PIT overflow value (PIV), enable the PIT, and enable
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* interrupts from the PIT.
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*/
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regval = PIT_PIV;
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DEBUGASSERT(regval <= PIT_MR_PIV_MASK);
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regval |= (PIT_MR_PITEN | PIT_MR_PITIEN);
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putreg32(regval, SAM_PIT_MR);
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/* And enable the timer interrupt */
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up_enable_irq(SAM_IRQ_PIT);
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}
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