40cd67eee6
Gregory Nutt has submitted the SGA and we can migrate the licenses to Apache. Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
282 lines
10 KiB
C
282 lines
10 KiB
C
/****************************************************************************
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* boards/arm/sam34/sam4l-xplained/include/board.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __BOARDS_ARM_SAM34_SAM4L_XPLAINED_INCLUDE_BOARD_H
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#define __BOARDS_ARM_SAM34_SAM4L_XPLAINED_INCLUDE_BOARD_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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# ifdef CONFIG_SAM34_GPIO_IRQ
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# include <arch/irq.h>
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# endif
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Clocking *****************************************************************/
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/* Select the DFLL as the source of the system clock.
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*
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* Options (define one):
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* BOARD_SYSCLK_SOURCE_RCSYS - System RC oscillator
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* BOARD_SYSCLK_SOURCE_OSC0 - Oscillator 0
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* BOARD_SYSCLK_SOURCE_PLL0 - Phase Locked Loop 0
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* BOARD_SYSCLK_SOURCE_DFLL0 - Digital Frequency Locked Loop
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* BOARD_SYSCLK_SOURCE_RC80M - 80 MHz RC oscillator
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* BOARD_SYSCLK_SOURCE_FCFAST12M - 12 MHz RC oscillator
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* BOARD_SYSCLK_SOURCE_FCFAST8M - 8 MHz RC oscillator
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* BOARD_SYSCLK_SOURCE_FCFAST4M - 4 MHz RC oscillator
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* BOARD_SYSCLK_SOURCE_RC1M - 1 MHz RC oscillator
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*/
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#define BOARD_SYSCLK_SOURCE_DFLL0 1
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/* Nominal frequencies in on-chip RC oscillators.
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* These are *not* configurable but appear here for use in frequency
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* calculations.
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* NOTE: These may frequencies may vary with temperature changes.
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*/
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#define BOARD_RCSYS_FREQUENCY 115000 /* Nominal frequency of RCSYS (Hz) */
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#define BOARD_RC32K_FREQUENCY 32768 /* Nominal frequency of RC32K (Hz) */
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#define BOARD_RC80M_FREQUENCY 80000000 /* Nominal frequency of RC80M (Hz) */
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#define BOARD_RCFAST4M_FREQUENCY 4000000 /* Nominal frequency of RCFAST4M (Hz) */
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#define BOARD_RCFAST8M_FREQUENCY 8000000 /* Nominal frequency of RCFAST8M (Hz) */
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#define BOARD_RCFAST12M_FREQUENCY 12000000 /* Nominal frequency of RCFAST12M (Hz) */
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#define BOARD_RC1M_FREQUENCY 1000000 /* Nominal frequency of RC1M (Hz) */
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/* The SAM4L Xplained Pro has two on-board crystals:
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* XC100 12MHz OSC0
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* XC101 32.768KHz OSC32
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*/
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/* OSC0 Configuration */
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#define BOARD_OSC0_FREQUENCY 12000000 /* 12MHz XTAL */
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/* OSC32 Configuration */
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#define BOARD_OSC32_FREQUENCY 32768 /* 32.768KHz XTAL */
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#define BOARD_OSC32_STARTUP_US 6100
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#define BOARD_OSC32_SELCURR BSCIF_OSCCTRL32_SELCURR_300
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#define BOARD_OSC32_ISXTAL 1 /* OSC32 is a crystal */
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/* Digital Frequency Locked Loop configuration
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* Fdfll = (Fclk * DFLLmul) / DFLLdiv
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* = 32768 * (48000000/32768) / 1 = 48MHz
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*
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* The actual frequency is 47.97MHz due to truncation of the multiplier.
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* The 48MHz target value is treated as "not-to-exceed" value). Use OSC0
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* if you need more accuracy (12MHz with a multiplier of 4).
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*
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* DFLL0 source options (select one):
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* BOARD_DFLL0_SOURCE_RCSYS - System RC oscillator
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* BOARD_DFLL0_SOURCE_OSC32K - 32.768KHz oscillator
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* BOARD_DFLL0_SOURCE_OSC0 - Oscillator 0
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* BOARD_DFLL0_SOURCE_RC80M - 80 MHz RC oscillator
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* BOARD_DFLL0_SOURCE_RC32K - 32 kHz RC oscillator
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*
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* NOTE: Nothing must be defined if the DFPLL is not used
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*/
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#define BOARD_DFLL0_SOURCE_OSC32K 1
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#define BOARD_DFLL0_TARGET 48000000
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#define BOARD_DFLL0_MUL (BOARD_DFLL0_TARGET / BOARD_OSC32_FREQUENCY)
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#define BOARD_DFLL0_DIV 1
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#define BOARD_DFLL0_FREQUENCY (BOARD_OSC32_FREQUENCY * BOARD_DFLL0_MUL / BOARD_DFLL0_DIV)
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/* Phase Locked Loop configuration
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* Fdfll = (Fclk * PLLmul) / PLLdiv
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*
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* PLL0 source options (select one):
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* BOARD_PLL0_SOURCE_OSC0 - Oscillator 0
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* BOARD_PLL0_SOURCE_GCLK9 - General clock 9
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*
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* BOARD_GLCK9_SOURCE_RCSYS - System RC oscillator
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* BOARD_GLCK9_SOURCE_OSC32K - Output from OSC32K
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* BOARD_GLCK9_SOURCE_DFLL0 - Output from DFLL0
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* BOARD_GLCK9_SOURCE_OSC0 - Output from Oscillator0
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* BOARD_GLCK9_SOURCE_RC80M - Output from 80MHz RCOSC
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* BOARD_GLCK9_SOURCE_RCFAST - Output from 4,8,12MHz RCFAST
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* BOARD_GLCK9_SOURCE_RC1M - Output from 1MHz RC1M
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* BOARD_GLCK9_SOURCE_CPUCLK - The CPU clock
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* BOARD_GLCK9_SOURCE_HSBCLK - High Speed Bus clock
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* BOARD_GLCK9_SOURCE_PBACLK - Peripheral Bus A clock
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* BOARD_GLCK9_SOURCE_PBBCLK - Peripheral Bus B clock
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* BOARD_GLCK9_SOURCE_PBCCLK - Peripheral Bus C clock
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* BOARD_GLCK9_SOURCE_PBDCLK - Peripheral Bus D clock
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* BOARD_GLCK9_SOURCE_RC32K - Output from 32kHz RCOSC
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*
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* NOTE: Nothing must be defined if the PLL0 is not used
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*/
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/* System clock dividers: Fbus = Fmck >> BUSshift */
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#define BOARD_CPU_SHIFT 0 /* Fcpu = Fmck = 48MHz */
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#define BOARD_PBA_SHIFT 0 /* Fpba = Fmck = 48MHz */
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#define BOARD_PBB_SHIFT 0 /* Fpbb = Fmck = 48MHz */
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#define BOARD_PBC_SHIFT 0 /* Fpbc = Fmck = 48MHz */
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#define BOARD_PBD_SHIFT 0 /* Fpbd = Fmck = 48MHz */
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/* Resulting frequencies */
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#define BOARD_MCK_FREQUENCY (BOARD_DFLL0_FREQUENCY)
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#define BOARD_CPU_FREQUENCY (BOARD_MCK_FREQUENCY >> BOARD_CPU_SHIFT)
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#define BOARD_PBA_FREQUENCY (BOARD_MCK_FREQUENCY >> BOARD_PBA_SHIFT)
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#define BOARD_PBB_FREQUENCY (BOARD_MCK_FREQUENCY >> BOARD_PBB_SHIFT)
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#define BOARD_PBC_FREQUENCY (BOARD_MCK_FREQUENCY >> BOARD_PBC_SHIFT)
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#define BOARD_PBD_FREQUENCY (BOARD_MCK_FREQUENCY >> BOARD_PBD_SHIFT)
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/* USBC.
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*
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* "The USBC has two bus clocks connected: One High Speed Bus clock
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* (CLK_USBC_AHB) and one Peripheral Bus clock (CLK_USBC_APB). These clocks
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* are generated by the Power Manager. Both clocks are enabled at reset
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* and can be disabled by the Power Manager. It is recommended to disable
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* the USBC before disabling the clocks, to avoid freezing the USBC in
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* an undefined state.
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*
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* "To follow the usb data rate at 12Mbit/s in full-speed mode, the
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* CLK_USBC_AHB clock should be at minimum 12MHz.
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*
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* "The 48MHz USB clock is generated by a dedicated generic clock from
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* the SCIF module. Before using the USB, the user must ensure that the
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* USB generic clock (GCLK_USBC) is enabled at 48MHz in the SCIF module."
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*
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* USB Generic Clock 7 (GCLK_USBC) source selection (one only)
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*
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* BOARD_USBC_SRC_OSC0
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* BOARD_USBC_SRC_PLL0
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* BOARD_USBC_SRC_DFLL
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* BOARD_USBC_SRC_GCLKIN0
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*/
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#define BOARD_USBC_SRC_DFLL 1 /* Source DFLL0 at 48MHz */
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#define BOARD_USBC_GCLK_DIV 1 /* Fusb = Fdfll / 1 = 48MHz */
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/* LED definitions **********************************************************/
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/* There are three LEDs on board the SAM4L Xplained Pro board: The EDBG
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* controls two of the LEDs, a power LED and a status LED. There is only
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* one user controllable LED, a yellow LED labelled LED0 near the SAM4L USB
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* connector.
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*
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* This LED is controlled by PC07 and LED0 can be activated by driving the
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* PC07 to GND.
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*/
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/* LED index values for use with board_userled() */
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#define BOARD_LED0 0
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#define BOARD_NLEDS 1
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/* LED bits for use with board_userled_all() */
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#define BOARD_LED0_BIT (1 << BOARD_LED0)
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/* When CONFIG_ARCH_LEDS is defined in the NuttX configuration, NuttX will
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* control LED0 as defined below. Thus if LED0 is statically on, NuttX has
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* successfully booted and is, apparently, running normally. If LED0 is
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* flashing at approximately 2Hz, then a fatal error has been detected and
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* the system has halted.
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*/
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#define LED_STARTED 0 /* LED0=OFF */
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#define LED_HEAPALLOCATE 0 /* LED0=OFF */
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#define LED_IRQSENABLED 0 /* LED0=OFF */
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#define LED_STACKCREATED 1 /* LED0=ON */
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#define LED_INIRQ 2 /* LED0=no change */
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#define LED_SIGNAL 2 /* LED0=no change */
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#define LED_ASSERTION 2 /* LED0=no change */
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#define LED_PANIC 3 /* LED0=flashing */
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/* Button definitions *******************************************************/
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/* QTouch button: The SAM4L Xplained Pro kit has one QTouch button.
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* The connection to the SAM4L is:
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*
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* PC13 CATB_SENSE15
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* PC14 CATB_DIS
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*/
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/* Mechanical buttons:
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*
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* The SAM4L Xplained Pro contains two mechanical buttons.
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* One button is the RESET button connected to the SAM4L reset line and the
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* other is a generic user configurable button.
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* When a button is pressed it will drive the I/O line to GND.
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*
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* PC24 SW0
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*/
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/* The SAM4l Xplained Pro supports one button: */
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#define BUTTON_SW0 0
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#define NUM_BUTTONS 1
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#define BUTTON_SW0_BIT (1 << BUTTON_SW0)
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/* Alternate Function Disambiguation ****************************************/
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/* USART0 is also available on connectors EXT1 and EXT4:
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*
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* EXT1 TXT4 GPIO Function
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* ---- ---- ------ -----------
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* 13 13 PB00 USART0_RXD
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* 14 14 PB01 USART0_TXD
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*/
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#define GPIO_USART0_RXD GPIO_USART0_RXD_4
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#define GPIO_USART0_TXD GPIO_USART0_TXD_4
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/* The SAM4L Xplained Pro contains an Embedded Debugger (EDBG) that can be
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* used to program and debug the ATSAM4LC4C using Serial Wire Debug (SWD).
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* The Embedded debugger also include a Virtual Com port interface over
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* USART1.
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* Virtual COM port connections:
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*
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* PC26 USART1 RXD
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* PC27 USART1 TXD
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*/
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#define GPIO_USART1_RXD GPIO_USART1_RXD_2
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#define GPIO_USART1_TXD GPIO_USART1_TXD_2
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/* SPI pins are brought out on EXT1 and EXT2 as:
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*
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* PA22 SPI/MOSI
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* PA21 SPI/MISO
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* PC30 SPI/SCK
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*/
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#define GPIO_SPI0_MISO GPIO_SPI0_MISO_1
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#define GPIO_SPI0_MOSI GPIO_SPI0_MOSI_1
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#define GPIO_SPI0_SPCK GPIO_SPI0_SPCK_4
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#endif /* __BOARDS_ARM_SAM34_SAM4L_XPLAINED_INCLUDE_BOARD_H */
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