567 lines
17 KiB
C
567 lines
17 KiB
C
/****************************************************************************
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* boards/arm/stm32/viewtool-stm32f107/src/stm32_ssd1289.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <sys/types.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <string.h>
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#include <assert.h>
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#include <errno.h>
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#include <debug.h>
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#include <nuttx/arch.h>
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#include <nuttx/board.h>
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#include <nuttx/lcd/lcd.h>
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#include <nuttx/lcd/ssd1289.h>
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#include <arch/board/board.h>
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#include "arm_arch.h"
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#include "stm32.h"
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#include "viewtool_stm32f107.h"
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#ifdef CONFIG_LCD_SSD1289
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Configuration ************************************************************/
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#ifndef CONFIG_STM32_FSMC
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# error "CONFIG_STM32_FSMC is required to use the LCD"
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#endif
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/* Color depth and format */
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#define LCD_BPP 16
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#define LCD_COLORFMT FB_FMT_RGB16_565
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/* Display Resolution */
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#if defined(CONFIG_LCD_LANDSCAPE)
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# define LCD_XRES 320
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# define LCD_YRES 240
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#else
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# define LCD_XRES 240
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# define LCD_YRES 320
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#endif
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#define LCD_BL_TIMER_PERIOD 8999
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/* LCD is connected to the FSMC_Bank1_NOR/SRAM1 and NE1 is used as chip
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* select signal
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*/
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/* RS <==> A16 */
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#define LCD_INDEX 0x60000000 /* RS = 0 */
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#define LCD_DATA 0x60020000 /* RS = 1 */
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/****************************************************************************
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* Private Function Prototypes
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****************************************************************************/
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/* Low Level LCD access */
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static void stm32_select(FAR struct ssd1289_lcd_s *dev);
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static void stm32_deselect(FAR struct ssd1289_lcd_s *dev);
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static void stm32_index(FAR struct ssd1289_lcd_s *dev, uint8_t index);
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#ifndef CONFIG_SSD1289_WRONLY
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static uint16_t stm32_read(FAR struct ssd1289_lcd_s *dev);
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#endif
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static void stm32_write(FAR struct ssd1289_lcd_s *dev, uint16_t data);
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static void stm32_backlight(FAR struct ssd1289_lcd_s *dev, int power);
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static void stm32_extmemgpios(const uint16_t *gpios, int ngpios);
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/* LCD
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*
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* An LCD may be connected via J11. Only the STM32F103 supports the FSMC
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* signals needed to drive the LCD.
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*
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* The LCD features an (1) HY32D module with built-in SSD1289 LCD controller,
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* and (a) a XPT2046 touch screen controller.
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*
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* LCD Connector
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* -------------
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*
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* ------------------------- --------------------- ---------------
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* Connector J11 GPIO CONFIGURATION(s)
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* PIN SIGNAL LEGEND (F103 only) LCD Module
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* --- --------- ----------- --------------------- ---------------
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* 1 VDD_5 NC N/A 5V ---
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* 2 GND GND N/A GND ---
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* 3 PD14 DATA0 GPIO_NPS_D0 D0 HY32D
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* 4 PD15 DATA1 GPIO_NPS_D1 D1 HY32D
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* 5 PD0 DATA2 GPIO_NPS_D2 D2 HY32D
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* 6 PD1 DATA3 GPIO_NPS_D3 D3 HY32D
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* 7 PE7 DATA4 GPIO_NPS_D4 D4 HY32D
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* 8 PE8 DATA5 GPIO_NPS_D5 D5 HY32D
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* 9 PE9 DATA6 GPIO_NPS_D6 D6 HY32D
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* 10 PE10 DATA7 GPIO_NPS_D7 D7 HY32D
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* 11 PE11 DATA8 GPIO_NPS_D8 D8 HY32D
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* 12 PE12 DATA9 GPIO_NPS_D9 D9 HY32D
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* 13 PE13 DATA10 GPIO_NPS_D10 D10 HY32D
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* 14 PE14 DATA11 GPIO_NPS_D11 D11 HY32D
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* 15 PE15 DATA12 GPIO_NPS_D12 D12 HY32D
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* 16 PD8 DATA13 GPIO_NPS_D13 D13 HY32D
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* 17 PD9 DATA14 GPIO_NPS_D14 D14 HY32D
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* 18 PD10 DATA15 GPIO_NPS_D15 D15 HY32D
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* 19 (3) LCD_CS GPIO_NPS_NE1 CS HY32D
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* 20 PD11 LCD_RS GPIO_NPS_A16 RS HY32D
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* 21 PD5 LCD_R/W GPIO_NPS_NWE WR HY32D
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* 22 PD4 LCD_RD GPIO_NPS_NOE RD HY32D
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* 23 PB1 LCD_RESET (GPIO) RESET HY32D
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* 24 N/C NC N/A TE (unused?)
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* 25 VDD_3.3 BL_VCC N/A BLVDD CA6219
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* (Drives LCD backlight)
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* 26 GND BL_GND N/A BLGND CA6219
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* 27 PB0 BL_PWM GPIO_TIM3_CH3OUT(2) BL_CNT CA6219
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* 28 PC5 LCDTP_IRQ (GPIO) TP_IRQ XPT2046
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* 29 PC4 LCDTP_CS (GPIO) TP_CS XPT2046
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* 30 PB13 LCDTP_CLK GPIO_SPI2_SCK TP_SCK XPT2046
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* 31 PB15 LCDTP_DIN GPIO_SPI2_MOSI TP_SI XPT2046
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* 32 PB14 LCDTP_DOUT GPIO_SPI2_MISO TP_SO XPT2046
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* 33 VDD_3.3 VDD_3.3 N/A 3.3V ---
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* 34 GND GND N/A GND ---
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* --- --------- ----------- --------------------- ---------------
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*
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* NOTES:
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* 1) Only the F103 version of the board supports the FSMC
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* 2) No remap
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* 3) LCD_CS is controlled by J13 JUMPER4 (under the LCD unfortunately):
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*
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* 1->2 : PD7 (GPIO_NPS_NE1) enables the multiplexor : 1E\ enable input
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* (active LOW)
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* 3->4 : PD13 provides 1A0 input (1A1 is grounded). : 1A0 address input
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* So will chip enable to either LCD_CS or
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* Flash_CS.
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* 5->6 : 1Y0 output to LCD_CS : 1Y0 address output
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* 7->8 : 1Y1 output to Flash_CE : 1Y1 address output
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*
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* Truth Table:
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* 1E\ 1A0 1A1 1Y0 1Y1
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* --- --- --- --- ---
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* HI N/A N/A HI HI
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* LO LO LO LO HI
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* LO HI LO HI LO
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*/
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const uint16_t fsmc_gpios[] =
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{
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/* A16... A23. REVISIT: only A16 is used by the LCD */
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GPIO_NPS_A16, GPIO_NPS_A17, GPIO_NPS_A18, GPIO_NPS_A19, GPIO_NPS_A20,
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GPIO_NPS_A21, GPIO_NPS_A22, GPIO_NPS_A23,
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/* D0... D15 */
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GPIO_NPS_D0, GPIO_NPS_D1, GPIO_NPS_D2, GPIO_NPS_D3, GPIO_NPS_D4,
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GPIO_NPS_D5, GPIO_NPS_D6, GPIO_NPS_D7, GPIO_NPS_D8, GPIO_NPS_D9,
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GPIO_NPS_D10, GPIO_NPS_D11, GPIO_NPS_D12, GPIO_NPS_D13, GPIO_NPS_D14,
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GPIO_NPS_D15,
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/* NOE, NWE, and NE1 */
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GPIO_NPS_NOE, GPIO_NPS_NWE, GPIO_NPS_NE1
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};
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#define NGPIOS (sizeof(fsmc_gpios)/sizeof(uint16_t))
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/* This is the driver state structure */
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static struct ssd1289_lcd_s g_ssd1289 =
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{
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.select = stm32_select,
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.deselect = stm32_deselect,
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.index = stm32_index,
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#ifndef CONFIG_SSD1289_WRONLY
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.read = stm32_read,
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#endif
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.write = stm32_write,
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.backlight = stm32_backlight
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};
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/* The saved instance of the LCD driver */
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static FAR struct lcd_dev_s *g_ssd1289drvr;
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: stm32_select
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*
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* Description:
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* Select the LCD device
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*
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****************************************************************************/
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static void stm32_select(FAR struct ssd1289_lcd_s *dev)
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{
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/* Does not apply to this hardware */
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}
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/****************************************************************************
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* Name: stm32_deselect
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*
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* Description:
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* De-select the LCD device
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*
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****************************************************************************/
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static void stm32_deselect(FAR struct ssd1289_lcd_s *dev)
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{
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/* Does not apply to this hardware */
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}
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/****************************************************************************
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* Name: stm32_index
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*
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* Description:
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* Set the index register
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*
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****************************************************************************/
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static void stm32_index(FAR struct ssd1289_lcd_s *dev, uint8_t index)
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{
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putreg16((uint16_t)index, LCD_INDEX);
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}
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/****************************************************************************
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* Name: stm32_read
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*
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* Description:
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* Read LCD data (GRAM data or register contents)
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*
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****************************************************************************/
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#ifndef CONFIG_SSD1289_WRONLY
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static uint16_t stm32_read(FAR struct ssd1289_lcd_s *dev)
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{
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return getreg16(LCD_DATA);
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}
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#endif
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/****************************************************************************
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* Name: stm32_write
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*
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* Description:
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* Write LCD data (GRAM data or register contents)
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*
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****************************************************************************/
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static void stm32_write(FAR struct ssd1289_lcd_s *dev, uint16_t data)
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{
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putreg16((uint16_t)data, LCD_DATA);
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}
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/****************************************************************************
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* Name: stm32_backlight
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*
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* Description:
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* Enable/disable LCD panel power
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* (0: full off - CONFIG_LCD_MAXPOWER: full on).
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* Used here to set pwm duty on timer used for backlight.
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*
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****************************************************************************/
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static void stm32_backlight(FAR struct ssd1289_lcd_s *dev, int power)
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{
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DEBUGASSERT(power <= CONFIG_LCD_MAXPOWER);
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/* Set new power level */
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if (power > 0)
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{
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uint32_t duty;
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/* Calculate the new backlight duty. It is a fraction of the timer
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* period based on the ration of the current power setting to the
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* maximum power setting.
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*/
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duty = ((uint32_t)LCD_BL_TIMER_PERIOD *
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(uint32_t)power) / CONFIG_LCD_MAXPOWER;
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if (duty >= LCD_BL_TIMER_PERIOD)
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{
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duty = LCD_BL_TIMER_PERIOD - 1;
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}
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putreg16((uint16_t)duty, STM32_TIM3_CCR2);
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}
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else
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{
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putreg16((uint16_t)0, STM32_TIM3_CCR2);
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}
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}
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static void init_lcd_backlight(void)
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{
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uint16_t ccmr;
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uint16_t ccer;
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/* Configure PB5 as TIM3 CH2 output */
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stm32_configgpio(GPIO_TIM3_CH2OUT);
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/* Enable timer 3 clocking */
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modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM3EN);
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/* Reset timer 3 */
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modifyreg32(STM32_RCC_APB1RSTR, 0, RCC_APB1RSTR_TIM3RST);
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modifyreg32(STM32_RCC_APB1RSTR, RCC_APB1RSTR_TIM3RST, 0);
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/* Reset the Counter Mode and set the clock division */
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putreg16(0, STM32_TIM3_CR1);
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/* Set the Autoreload value */
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putreg16(LCD_BL_TIMER_PERIOD, STM32_TIM3_ARR);
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/* Set the Prescaler value */
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putreg16(0, STM32_TIM3_PSC);
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/* Generate an update event to reload the Prescaler value immediately */
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putreg16(ATIM_EGR_UG, STM32_TIM3_EGR);
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/* Disable the Channel 2 */
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ccer = getreg16(STM32_TIM3_CCER);
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ccer &= ~ATIM_CCER_CC2E;
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putreg16(ccer, STM32_TIM3_CCER);
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/* Select the Output Compare Mode Bits */
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ccmr = getreg16(STM32_TIM3_CCMR1);
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ccmr &= ATIM_CCMR1_OC2M_MASK;
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ccmr |= (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC2M_SHIFT);
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putreg16(0, STM32_TIM3_CCR2);
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/* Select the output polarity level == HIGH */
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ccer &= !ATIM_CCER_CC2P;
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/* Enable channel 2 */
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ccer |= ATIM_CCER_CC2E;
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/* Write the timer configuration */
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putreg16(ccmr, STM32_TIM3_CCMR1);
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putreg16(ccer, STM32_TIM3_CCER);
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/* Set the auto preload enable bit */
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modifyreg16(STM32_TIM3_CR1, 0, ATIM_CR1_ARPE);
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/* Enable Backlight Timer !!!! */
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modifyreg16(STM32_TIM3_CR1, 0, ATIM_CR1_CEN);
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/* Dump timer3 registers */
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lcdinfo("APB1ENR: %08x\n", getreg32(STM32_RCC_APB1ENR));
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lcdinfo("CR1: %04x\n", getreg32(STM32_TIM3_CR1));
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lcdinfo("CR2: %04x\n", getreg32(STM32_TIM3_CR2));
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lcdinfo("SMCR: %04x\n", getreg32(STM32_TIM3_SMCR));
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lcdinfo("DIER: %04x\n", getreg32(STM32_TIM3_DIER));
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lcdinfo("SR: %04x\n", getreg32(STM32_TIM3_SR));
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lcdinfo("EGR: %04x\n", getreg32(STM32_TIM3_EGR));
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lcdinfo("CCMR1: %04x\n", getreg32(STM32_TIM3_CCMR1));
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lcdinfo("CCMR2: %04x\n", getreg32(STM32_TIM3_CCMR2));
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lcdinfo("CCER: %04x\n", getreg32(STM32_TIM3_CCER));
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lcdinfo("CNT: %04x\n", getreg32(STM32_TIM3_CNT));
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lcdinfo("PSC: %04x\n", getreg32(STM32_TIM3_PSC));
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lcdinfo("ARR: %04x\n", getreg32(STM32_TIM3_ARR));
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lcdinfo("CCR1: %04x\n", getreg32(STM32_TIM3_CCR1));
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lcdinfo("CCR2: %04x\n", getreg32(STM32_TIM3_CCR2));
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lcdinfo("CCR3: %04x\n", getreg32(STM32_TIM3_CCR3));
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lcdinfo("CCR4: %04x\n", getreg32(STM32_TIM3_CCR4));
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lcdinfo("CCR4: %04x\n", getreg32(STM32_TIM3_CCR4));
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lcdinfo("CCR4: %04x\n", getreg32(STM32_TIM3_CCR4));
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lcdinfo("DMAR: %04x\n", getreg32(STM32_TIM3_DMAR));
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}
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/****************************************************************************
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* Name: stm32_selectlcd
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*
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* Description:
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* Initialize the memory controller (FSMC)
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*
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****************************************************************************/
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static void stm32_selectlcd(void)
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{
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/* Configure new GPIO state */
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stm32_extmemgpios(fsmc_gpios, NGPIOS);
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/* Enable AHB clocking to the FSMC */
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stm32_fsmc_enable();
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/* Bank1 NOR/SRAM control register configuration */
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putreg32(FSMC_BCR_SRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR1);
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/* Bank1 NOR/SRAM timing register configuration */
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putreg32(
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FSMC_BTR_ADDSET(1) | FSMC_BTR_ADDHLD(0) |
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FSMC_BTR_DATAST(2) | FSMC_BTR_BUSTURN(0) |
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FSMC_BTR_CLKDIV(0) | FSMC_BTR_DATLAT(0) |
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FSMC_BTR_ACCMODA,
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STM32_FSMC_BTR1);
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/* As ext mode is not active the write timing is ignored!! */
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putreg32(0xffffffff, STM32_FSMC_BWTR1);
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/* Enable the bank by setting the MBKEN bit */
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putreg32(FSMC_BCR_MBKEN | FSMC_BCR_SRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN,
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STM32_FSMC_BCR1);
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/* Configure the LCD RESET pin.
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* Initial value will take the LCD out of reset
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*/
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stm32_configgpio(GPIO_LCD_RESET);
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}
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/****************************************************************************
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* Name: stm32_extmemgpios
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*
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* Description:
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* Initialize GPIOs for NOR or SRAM
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*
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****************************************************************************/
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static void stm32_extmemgpios(const uint16_t *gpios, int ngpios)
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{
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int i;
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/* Configure GPIOs */
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for (i = 0; i < ngpios; i++)
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{
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stm32_configgpio(gpios[i]);
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}
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: board_lcd_initialize
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*
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* Description:
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* Initialize the LCD video hardware.
|
|
* The initial state of the LCD is fully initialized, display memory
|
|
* cleared, and the LCD ready to use, but with the power setting at 0
|
|
* (full off).
|
|
*
|
|
****************************************************************************/
|
|
|
|
int board_lcd_initialize(void)
|
|
{
|
|
/* Only initialize the driver once */
|
|
|
|
if (!g_ssd1289drvr)
|
|
{
|
|
lcdinfo("Initializing\n");
|
|
|
|
/* Initialize the backlight */
|
|
|
|
init_lcd_backlight();
|
|
|
|
/* Configure GPIO pins and configure the FSMC to support the LCD */
|
|
|
|
stm32_selectlcd();
|
|
|
|
/* Configure and enable the LCD */
|
|
|
|
up_mdelay(50);
|
|
g_ssd1289drvr = ssd1289_lcdinitialize(&g_ssd1289);
|
|
if (!g_ssd1289drvr)
|
|
{
|
|
lcderr("ERROR: ssd1289_lcdinitialize failed\n");
|
|
return -ENODEV;
|
|
}
|
|
}
|
|
|
|
/* Turn the display off */
|
|
|
|
g_ssd1289drvr->setpower(g_ssd1289drvr, 0);
|
|
return OK;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: board_lcd_getdev
|
|
*
|
|
* Description:
|
|
* Return a a reference to the LCD object for the specified LCD.
|
|
* This allows support for multiple LCD devices.
|
|
*
|
|
****************************************************************************/
|
|
|
|
FAR struct lcd_dev_s *board_lcd_getdev(int lcddev)
|
|
{
|
|
DEBUGASSERT(lcddev == 0);
|
|
return g_ssd1289drvr;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: board_lcd_uninitialize
|
|
*
|
|
* Description:
|
|
* Uninitialize the LCD support
|
|
*
|
|
****************************************************************************/
|
|
|
|
void board_lcd_uninitialize(void)
|
|
{
|
|
/* Turn the display off */
|
|
|
|
g_ssd1289drvr->setpower(g_ssd1289drvr, 0);
|
|
}
|
|
|
|
#endif /* CONFIG_LCD_SSD1289 */
|